Onkyo TX-SA805 - Page 149

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -75
Q103 : F2628E-01 (XM Digital Transceiver)
BLOCK DIAGRAM
PIN CONFIGURATION
TX-SR805/SA805
SAII
I2S_OCLK (M=o, S=n/u)
I2S_LRCLK (M=o; S=i)
I2S_SCLK (M=o; S=i)
I2S_DATA (M=o; S=i)
I2S_RATE (M=o, S=n/u)
MUTE (M=o, S=n/u)
HSDP_EN# (M=o; S=i)
HSDP_CLK (M=o; S=i)
HSDP_DATA (M=o; S=i)
LSDP (M=o; S=i)
SAII_REQ (M=i; S=o)
SAII_CLK (M=o; S=i)
SAII_DATA (M=o; S=i)
SC_RX_IN (M=i, S=i)
SC_TX_OUT (M=o, S=o)
SC_RATE (M=i, S=o)
OSC_OUT
RAM
OSC_IN
OSC
RESET# (M=i, S=i)
ANT_REV (M=o,S=n/u)
DT4_MODE (M=i, S=i)
SLAVE_SEL (M=i, S=i)
TEST (M=i, S=i)
(RFU –I2C_SCL)
(RFU –I2C_SDA)
GND
3.3V
Inter-IC
Sound
(I2S)
High Speed
Data Port
(HSDP)
Low Speed
Data Port
(LSDP)
Sys Ctrlr
(CBM)
Bus I/F
Misc Status
& Control
COMM ENGINE
COMM I/F
COMM_TX_EN (M=o, S=o)
LINKACTIVE (M=o, S=o)
COMM_TX_P
COMM_TX_M
COMM_RX_P
COMM_RX_M
13 14
15
16 17 18
19
20
21
22
23
24
I2S_RATE
LINKACTIVE
COMM_RX_P
COMM_RX_M
COMM_TX_M
COMM_TX_P
VDD
VDD
VSS
VSS
VSS
COMM_TX_EN
1
2
3
4
5
6
7
8
9
10
11
12
LSDP
SC_TX_OUT
SC_RX_IN
RFU (I2C_SDA)
ANT_REV
RESET#
SLAVE_SEL
VDD
VDD
VSS
RFU (I2C_SCL)
VSS
XM/DT IC
42 38
I2S_DATA I2S_SCLK I2S_LRCLK
I2S_OCLK
SAII_CLK SAII_DATA SAII_EN VDD VDD
VSS
VSS MUTE
48
47
46
45
44 43 41 40 39 37
OSC_OUT
OSC_IN
TEST
HSDP_DATA
HSDP_CLK
VDD
VDD
VSS
SC_RATE
VSS
34
33
32
31
30
29
28
27
26
25
HSDP_EN#
36
DT4_MODE
35