Panasonic FPG-C32T2H - Page 367

12-75
Num-
ber
Name Boolean Operand Description Steps
F37
P37
16-bit data
decrement
-1
P-1
D(D)-1→(D) 3
F38
P38
32-bit data
decrement
D-1
PD-1
D (D+1, D)-1→(D+1, D) 3
F39
P39
32-bit data
multiplication
(result in 32
bits)
D*D
PD*D
S1, S2, D (S1+1, S1)x(S2+1, S2)→(D+1, D) 11
BCD arithmetic instructions
F40
P40
4-digit
BCD data
addition
B+
PB+
S, D (D)+(S)→(D) 5
F41
P41
8-digit
BCD data
addition
DB+
PDB+
S, D (D+1, D)+(S+1, S)→(D+1, D) 7
F42
P42
4-digit
BCD data
addition
B+
PB+
S1, S2, D (S1)+(S2)→(D) 7
F43
P43
8-digit
BCD data
addition
DB+
PDB+
S1, S2, D (S1+1, S1)+(S2+1, S2)→(D+1, D) 11
F45
P45
4-digit
BCD data
subtraction
B-
PB-
S, D (D)-(S)→(D) 5
F46
P46
8-digit
BCD data
subtraction
DB-
PDB-
S, D (D+1, D)-(S+1, S)→(D+1, D) 7
F47
P47
4-digit
BCD data
subtraction
B-
PB-
S1, S2, D (S1)-(S2)→(D) 7