Panasonic SA-PM65MD - Page 46

Pin
No.
Mark I/O Function
42 TEST04 O Test signal output terminal
(Not used, open)
43 TEST05
44 CFSYNC I ATRACK management
frame simultaneous signal
input terminal
45 TEST06 O Test signal output terminal
(Not used, open)
46 TEST07 I Connected to rec/play
switch signal
47 TOK OK O Not used, open
48 HF ON — Drive signal output
terminal to Q3 (POWER
SUPPLY CONTROL)
49 PANEL
CLK
I Panel I/F clock input
terminal
50 PANEL
DATA I
I Panel I/F data input terminal
51 PANEL
DATA 0
O Panel I/F data output
terminal
52 PANEL
CS
O Panel I/F chip select output
terminal
53 SELAD O Micro computer I/F address
select output terminal
54 SSCLK O Micro computer I/F clock
output terminal
55 SSDR I Micro computer I/F reading
data input terminal
56 SSDW O Micro computer I/F writing
data output terminal
57 LCDCK O LCD clock test signal
output terminal (Connected
to power supply through
resistor)
58 ADRS
TEST
RXD
O Test signal output terminal
(Connected to power
supply through resistor)
59 LCD
DATA
TXD
O Test signal output terminal
(Not used, open)
60 VREF- — Connected to GND
61 TEMP I Temprature sensor amp
input terminal
62 KEY1 I Key input 1 terminal
63 KEY2 I Key input 2 terminal
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