Philips DCC170/00 - Page 66

o
Q601
SAA2O13
ADAS
LiCNTI
LïCNTO
L3MOOEM
L3CLKM
L3DATAM
VSS
LTCNT1
C
LTCNTOC
L3MO0EC
L3CLKC
L3DATAC
o.
OF
Eg,,u2
22
=
È
H
F
"Ë
È
É
FDAO
FDCL
FDWS
PWRDWN
Tl0
POR
LOWPWR
CLK24
VSS
VDD
RESET
hon
ADAS)
t output
rtor output
Éor
input
letors)
rtors)
noutput
r
input
:output
PFoCeSSlng
rve
Processrng
rcc
output
rce
output
rce output
,to
DAC
IDAIO and
ADC
n
ertcraal
source
reraple
frequeney
'DAIO
Ësation
rADAS)
E 0 E
3
=
E
F
E
2::
F
ócncn
IJJ
IIJ
\.,,
G cE
z
z
o
t-
cn
z
H
=Í
otr
oo
ALLOCATION
AND
SCALE FACTOR
COMPUTATION
Pin
Name
vo
Function
Notes
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
15
17
18
1g
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
35
37
38
39
40
41
42
43
44
LOWPWR
POR
Tt0
PWRDWN
FDWS
FDCL
FDAO
FDAI
FSYNC
FRESET
FDIR
sFc3coM
P
FS256
VDD
NC
NC
NC
VSS
I
I
I
I
vo
o
o
o
o
vo
o
o
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
vo
t/o
I
I
I
I
I
supply
ground
24.576 MHz
clock input
Low
power
playback
select
Power
On
Reset
(test
input)
connect
to VSS
power
down
input
word
select
filtered-l25
(F-l25)
bus
bit clock F-t25
bus
output
data
F-l2S
bus
input
data
F-l2S
bus
subband
synchronisation
on
F-l2S
bus
reset
signal
from
codec
F-l25
bus direction
SFC3
(SAA2003)
compatibitity
mode
system
clock,256
x
sample
fiequency
positive
supply
(not
connected)
(not
connected)
(not
connected)
supply
ground
(1)
(1)
(2)
(1)
(1)
(2)
(3)
(3)
(2)
(2)
-64-