Philips for Intel Socket 775 processor - Page 28

Block Diagrams, Testpoint Overview, and Waveforms
EN 28 S/SD/HD 3.1 PDP6.
42" HDv3
S37" SDv4
1024× 768 Pixels
1024× 3× 768 Cells
YPulse
Generator
Row
Driver
VsVa
Vcc
Vsync
Enable
Hsync
DCLK
DRAM
Display
Data
Driver
Timing Controller
Driver
Timing
Scan
Timing
Vdd
DATA_R
8Bits
Column Driver
LOGIC CONTROL
DRIVER CIRCUIT & PANEL
DATA_G
8Bits
DATA_B
8Bits
Input Data Processor
Data Controller
XPulse
Generator
Vset Vsc
Ve
LVDS
Interface
Column Driver
- Vcc : Voltage for Logic Control
- Vdd : Voltage for Fet driver
- Va : Voltage for address pulse
- Vs : Voltage sustain pulse
- Vsc : Voltage for scan pulse
- Ve : Voltage for X ramp pulse
- Vset : Voltage for Y ramp pulse
Reference
- Vcc : Voltage for Logic Control
- Vdd : Voltage for FET driver
- Va : Voltage for address pulse
- Vs : Voltage sustain pulse
- Vsc : Voltage for scan pulse
- Ve : Voltage for X ramp pulse
- Vset : Voltage for Y ramp pulse
Reference
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Enable
Hsync
DCLK
k
k
k
{
z
{
}
} }
}
LVDS
Interface
Data Controller
Input Data Processor
Driver
Timing Controller
DRAM
Row
Driver
Y Pulse
Generator
852 x 480 Pixels
852 x 3 x 480 Cells
Column Driver
X Pulse
Generator
DRIVER CIRCUIT & PANEL
LOGIC CONTROL
DATA_R
8 Bits
DATA_G
8 Bits
DATA_B
8 Bits
Vsync