Philips FW-V537 - 3 CDC-LC - CIRCUIT DIAGRAM (PART 2); Signal Processor and Audio Circuits

10-910-9
voltage stab.
100R
3769
6807
BZX284
C3V9
6811
1N4003
3767
33R
BC847B
7815
+5V
SW_INFO
+10V
SHR_CL
SHR_DATA
SHR_STR
+3.3V
3CDC-LC
part 2
communication with
Shift Register
on part 3
communication with
Front microprocessor
KILL
TIMING
BITSTREAM DAC
SER. DATA INTERFACE
VERSAT.
INTERF.
EBU
INTERF.
CORR. ERROR
CONTROL
FUNCTION
PRE-
PROCESSING
AUDIO
PROCESSOR
MICROCONTROLLER
INTERFACE
SUBCODE
PROCESSOR
ADDR
SRAM
PEAK
DET.
MOTOR
CONTROL
OUTPUT
STAGES
DIG.
PLL
EFM
DEMOD
VERSATILE INTERFACE
ANALOG / DIGITAL
CONVERTER
VREF GEN.
FRONTEND
from part11801
Signal Processor
4
VSSA2
14
VSSD1
33
VSSD2
50
VSSD3
58
WCLI
35
WCLK
28
SUB
46
TEST1
25
TEST2
31
TEST3
44
V1
63
V2|V3
34
V4
61
V5
62
VDDA1
5
VDDA2
17
VDDD1P
52
VDDD2C
57
VNEG
20
VPOS
21
VRIN
7
VSSA1
RAB
RCK
45
RESET
38
RN
22
RP
23
SBSY
48
SCL
40
SCLI
37
SCLK
29
SDA
39
SDI
36
SELPLL
24
SFSY
47
SILD
42
56
SL
STATUS
43
FO
55
HFIN
2
HFREF
1
IREF
6
ISLICE
3
KILL
32
LDON
64
LN
18
LP
19
MOTO1
59
MOTO2
60
R1
12
R2
13
RA
54
41
SAA7324/SAA7325
CFLG
53
CL11|4
49
CL16
26
CRIN
16
CROUT
15
D1
8
D2
9
D3
10
D4
R1
R2
D1 D2 D3 D4
11
DATA
27
DOEM
51
30
EF
7802
10K (4x)
3819
470R
470R
2843
100n
+3.3V
3865
120R
22K
3828
3810
470R
15R
3855
+3.3V
2826
47u
2823
68p
120R
3862
AT-49
1810
2818
1n5
2833
33p
+3.3V
10K
3809
+3.3VPORE
+3.3V
3812
470R
27p
2829
1n
2820
33p
3804
10K
+3.3V
3832
10K
1n5
2816
470R
27K
3827
+3servo
4u7
Innersw
LDON
RAB
SDA
PORE
SICL SILD
SL
M1
FO
RA
2834
2824
3826
22K
470R
3853
2813
100R
3864
3867*
220K
2838
10u
+3.3V
2837
47n
HF
VrefCD10
3823
1K
PHOTO DIODES
CD DRIVE on PART1
TO SERVO/MOTOR DRIVER
on PART1
+3.3V
SERIAL DATA
LOOPBACK
INTERFACE
PORE
1.7V 1.7V
3.2V
1.7V
3.2V
3.2V
3.4V
3V
3V
1.6V 1.6V1.6V 1.6V 1.6V 1.6V1.6V1.6V1.6V
3.2V
0.8V3.2V
TB = 0.5µs/div
800mVpp
EYE-PATTERN
RW/DA
to part1 7801/pin11
10K
3849
3813
3814
3858*
3861
3717
1R
3759
470R
3716
100R
3712
10R
EBU
* marked components only forseen
6812
BAS316
+3.3V
A
B
C
D
E
12 13 14
12345678
C
D
E
F
G
H
I
91011121314
F
G
B
A
1234567891011
H
I
3.3V
4.1V
. . . V DC voltages measured in
PLAY MODE
with following conditions:
"+10V" = 10V
"+5V" = 5V
EVM
V
DSA_ACK
EBU/GND
LEFT
SDA
GND
SILD
GND
GND
CD_IIS_DATA
SICL
GND
RAB
EBU_GND
RIGHT
IIS_WCLK
IIS_SCLK
DSA_STB
CD10_RESETn
GND
5V
GNDA
DSA_DATA
DSA_ACK
DSA_STB
DSA_DATA
1802
-STKFMN
CD_IIS_DATA
220R
220R
3881
IIS_WCLK
3878
IIS_SCLK
10K
SDA
+5V
RESET
SICL
SILD
RAB
3777
communication
Front µP - VCD Module
communication
VCD Module - Signal processor
DIGITAL AUDIO
DSA_ACK
DSA_STB
DSA_DATA
CD_IIS_DATA
IIS_SCLK
IIS_WCLK
0V
SDA
5V
3CDC-LC Herman Mainboard Sheet2 2001-10-15 (VCD Version)
EBU
SDA
RESET
SICL
SILD
RAB
EBU
DOBM
ANALOG AUDIO
ANALOG AUDIO
1802 B14
1805 F14
1810 B6
2813 A3
2816 D7
2818 C7
2820 G5
2822 A3
2823 B3
2824 B3
2826 D3
2829 G5
2833 B6
2834 B6
2837 B4
2838 A4
2843 C7
2845 C7
2854 I12
2865 I13
2870 I5
2871 H6
2874 H11
3701 I5
3705 H7
3706 I7
3707 I7
3711 I7
3712 G2
3712 I13
3716 F2
3717 G2
3718 H6
3730 I4
3731 I5
3732 I5
3733 I5
3734 I5
3759 F2
3759 H10
3767 E11
3769 F11
3774 H8
3777 D9
3804 F7
3808 I7
3809 B2
3810 G5
3812 F5
3813 F5
3814 F4
3816 E7
3817 E7
3818 E7
3819 G5
3823 A4
3825 A3
3826 B3
3827 B4
3828 B3
3832 G6
3849 F6
3853 A4
3855 D2
3858 G4
3859 G4
3860 G4
3861 G4
3862 B7
3864 A4
3865 D7
3867 A4
3878 E13
3881 E13
4808 C14
5800 I12
6807 F11
6809 H7
6811 G11
6812 B2
7802 C5
7815 F11
7816 I5
10n
1n5
0u47
2845
100R
3818
470R
3817
470R
3816
EQSEL
to part1 7801
+5V
14
8
7
6
9
5
4
3
2
19
18
13
17
22
21
20
1
10
12
11
16
15
HF_DETECT
from 7821/C on part1
3825
1K
2822
2n2
1805
7
8
2
6
1
4
3
5
9
12
10
11
15
14
13
DSA_ACK
DSA_STB
SHR_STR
SHR_DATA
LEFT
GND
GND
GNDA
RIGHT
DSA_DATA
+10
SW_INFO
SHR_CL
+5V
GND
3860
3859*