Circuit Descriptions, Abbreviation List, and IC Data Sheets
EN 146 LC4.31E AA9.
9.5.3 Diagram B7+B8+B9, Type GM1501 (IC7801, Genesis)
Figure 9-5 Internal block diagram and pin configuration
In fra- red R x Lo w
n d w i d
D C
B a t h
A
Pul se W i dth
M odul ator
DDC2Bi
DVI
8/ 16 bi t v i deo
4: 2: 2/CCIR656
8/16 /24 b i t
v i deo
( 4 :4 :4 / 4 :2 :2 /
CCIR656)
Test Patte rn
Gen e rato r
Ul tr a-Rel i abl e
DVI Rx
D V I-C o mp lian t
I nput
T r ip le A D C
and PLL
14.318 M H z
Cr y s tal
Reference
Image
Captur e
and
M easu re
ment
RealColor
TM
Gr aphi cs
Shrink
F ilte r
Clock
Gener a ti on
Frame
Store
Contr o l
JT A G
GP IO
2- w i re
Serial I/F
Externa l
ROM I/ F
In tern a l
ROM
TTL/
LVDS
Tx
Di spl a y
Ti mi ng
Gen e rato r
OSD
C o n t ro lle r
Color Table
RA M s
Output
Bl ender
Vi deo
Shrink
F ilte r
M o ti on
Ad a p t .
3: 2/2: 2
detecti on
Vi deo
Zoom
F ilte r
Gr aphi cs
Zoom
F ilte r
Image
Captur e
and
M easu re
ment
Int e rnal
RA M
X186
Mi c r o -
co n t ro lle r
Interfa ce
Para lle l
ROM
IF /exte r n a l
mic r o
A n al og RGB
I nput
Panel Data
/C o n t ro l
DDC2Bi
analog
DDR SDR A M
I/F
Block Diagram
Pin Configuration
A
NC
ADC_3.3 ADC_1.8 ADC_1.8
A DC_ DGND
RX C+ DVI _ GND RX 0 + R X 1 + R X 2 + DVI _ GND LBADC_I N 3 D_GND
B
B L U E - B L U E +
ADC_3.3
A DC_ DGND
DVI _ GND RX C- DVI _ GND RX 0 - R X 1 - R X 2 - REX T LBADC_I N 2 D_GND
C
G R E E N - G R E E N + S O G
ADC_AGND NC DVI_3.3 DVI _ GND DVI_3.3 DVI_3.3 DVI_3.3 DVI_3.3 LBADC_I N 1 LBADC_33
D
R E D - R E D +
ADC_3.3 ADC_AGND NC DVI_1.8 DVI _ GND DVI_1.8 DVI_1.8 DVI_1.8 DVI _ GND
LBADC_
RETURN
L B A DC_ GND
E
ADC_AGND ADC_AGND ADC_3.3 ADC_AGND
F
NC
VDDD33_
PLL
VSSA33_
RPLL
VDDA33_
RPLL
G
VDDA33_
FPLL
VSSD33_
PLL
T C L K X T A L
H
VDDD33_
SDDS
VSSA33_
SDDS
VDDA33_
SDDS
VSSA33_
FPLL
J
VDDD33_
DDDS
VSSA33_
DDDS
VDDA33_
DDDS
VSSD33_
SDDS
K
RESETn
ACS_
RSET_HD
NC
VSSD33_
DDDS
CORE_1.8 CORE_1. 8 D_GND D_GND
L
O C M _ I N T 2 O C M _ I N T 1 AVSY NC AHSY NC
D_GND CORE_1. 8 D_GND D_GND
M
O C M _ U D O O C M _ U D I I R 0 I R 1
D_GND D_GND D_GND D_GND
N
V G A _ S D A V G A _ S C L D V I _ S D A D V I _ S C L
D_GND D_GND D_GND D_GND
P
O C M _ C S 1 n O C M _ C S 2 n MSTR_SDA MSTR_SCL
D_GND D_GND D_GND D_GND
R
R O M _ C S n O C M _ R E n OCM_ W E n EX T C L K
D_GND D_GND D_GND D_GND
T
OCMADDR
17
OCMADDR
18
OCMADDR
19
OCM_CS0n
D_GND CORE_1. 8 D_GND D_GND
U
OCMADDR
13
OCMADDR
14
OCMADDR
15
OCMADDR
16
CORE_1.8 CORE_1. 8 D_GND D_GND
V
OCMADDR
9
OCMADDR
10
OCMADDR
11
OCMADDR
12
W
OCMADDR
6
OCMADDR
7
OCMADDR
8
IO_3 .3
Y
OCMADDR
3
OCMADDR
4
OCMADDR
5
IO_3 .3
AA
OCMADDR
0
OCMADDR
1
OCMADDR
2
IO_3 .3
AB
OC M D AT A1 3 O C M D AT A1 4 OC M D AT A1 5
IO_3 .3
AC
OC M D AT A1 0 O C M D AT A1 1 OC M D AT A1 2
IO_3 .3
G P IO _ G 09_ B2
(
DE GRN0
)
IO_3 .3 DCLK IO_3 .3
G P IO _ G 07_ B2
(
DE RE D4
)
IO_3 .3
SHIELD[1 ]
(DE G RN3 )
LVDSB_3.3
LVD SB_ GN D
AD
O C M D A T A 9 O C M D A T A 6 O C M D A T A 3 O C M D A T A 0
G P IO _ G 09_ B3
(
DE GRN1
)
G P IO _ G 08_ B0
(
DORE D0
)
DEN
G P IO _ G 08_ B5
(
DOB L U1
)
G P IO _ G 07_ B3
(
DE RE D5
)
G P IO _ G 07_ B6
(
DE RE D8
)
SHIELD[2 ]
(DE G RN4 )
LVDSB_3.3 LVDSB_3.3
AE
O C M D A T A 8 O C M D A T A 5 OCMDATA2
G P IO _ G 09_ B0
(
DE RE D0
)
G P IO _ G 09_ B4
(
D EBLU 0
)
G P IO _ G 08_ B1
(
DORE D1
)
G P IO _ G 08_ B3
(
DOGRN1
)
G P IO _ G 07_ B0
(
DE RE D2
)
G P IO _ G 07_ B4
(
DE RE D6
)
G P IO _ G 07_ B7
(
DE RE D9
)
SHIELD[3 ]
(DE G RN5 )
BC +
(DE G RN8 )
SHIELD[4 ]
(DE B L U2 )
AF
O C M D A T A 7 O C M D A T A 4 OCMDATA1
G P IO _ G 09_ B1
(
DE RE D1
)
G P IO _ G 09_ B5
(
D EBLU 1
)
G P IO _ G 08_ B2
(
DOGRN0
)
G P IO _ G 08_ B4
(
DOB L U0
)
G P IO _ G 07_ B1
(
DE RE D3
)
G P IO _ G 07_ B5
(
DE RE D7
)
SHIELD[0 ]
(DE G RN2 )
B3+
(DE G RN6 )
B3-
(DE G RN7 )
BC -
(DE G RN9 )
1 2 3 4 5 6 7 8 9 1 0 11 12 1 3
E_14490_099.eps
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