Pilz PSS CPU Series - Technical Details; Electrical Data; Program Memory Specifications; Display and Interfaces

7Operating Manual
ENGLISH
Program memory failsafe section PSS CPU, PSS1 CPU, PSS SF CPU,
PSS1 SF CPU:
64 KByte integral Flash memory
PSS CPU 2, PSS1 CPU 2, PSS SB CPU,
PSS1 SB CPU:
256 KByte integral Flash memory
Program memory standard section PSS CPU, PSS1 CPU, PSS SF CPU,
PSS1 SF CPU: Cartridge with 256/512 KByte
Flash memory or RAM
PSS CPU 2, PSS1 CPU 2, PSS SB CPU,
PSS1 SB CPU:
512 KByte integral Flash memory
Display Four-digit
Interfaces PSS CPU, PSS1 CPU, PSS SF CPU,
PSS1 SF CPU, PSS SB CPU, PSS1 SB CPU:
RS 485 for programming device and
RS 232 for user, galvanically isolated
PSS CPU 2, PSS1 CPU 2:
RS 232/RS485 for programming device and
for user, galvanically isolated
PSS SB CPU, PSS1 SB CPU:
SafetyBUS p interface
SafetyBUS p (PSS SB CPU and PSS1 SB CPU)
Communication speed Max. 500 kBaud
Cable runs Max. 3000 m
Communication type Differential two-wire circuit
Connection 9-pin D-Sub connector
Environmental Data
Protection type (EN 60529, 10/91) IP 20 (installed on module rack)
Mounting position Vertical on module rack
Ambient temperature (DIN IEC 68-2-14, 06/87) 0 ... 60 °C
Storage temperature (EN 60068-2-1/-2, 03/93) -25 ... +70 °C
Relative humidity
(DIN IEC 68-2-30, 09/86) Max. 95 % r.h.
Condensation Not permitted
Vibration (EN 60068-2-6, 04/95) Frequency range: 10 ... 100 Hz
Amplitude: 0.1 mm, max. 3g
Shock (DIN IEC 68-2-29) 30g, 11 ms/10g, 16 ms