Pioneer PDP-R03E - Pc I;F Block Diagram

A
B
C
D
1
23
4
1234
16
PDP-R03E
V0
A/D
Amp
PLL
IC4
CXA3506R
I
2
C=CH2
5V->3.3V Reg
IC8 PQ20VZ11
X4
25MHz
CVIC
IC25
V1
A/D
IC310
TLC5733A
12V->5VReg
IC7 PQ05TZ11
PC_ C3
HV SEL
OV0 _H
V1
PLL
IC328
TLC2933IPW
12V->9V R eg
IC415 BA09FP
OV0_CLP
CPCI-00 56CE
V0
Sync
Sel
IC411
74LCX157
1B
2B
4B
1A
2A
4A
-A /+B
1Y
2Y
4Y
CN8
7
9
10
PC _H
PC_V
PC_C
CN6
18
17
29,3
0
MAIN _H
D
MAIN_VD
5
1
3
PC_R
RIN2
GIN2
BIN2
PC _G
PC_B
RIN1
GIN1
BIN1
25,2
6
21,2
2
MAI N_
B
MAI N_
G
MAI N_
R
ROUT
GOUT
BOUT
SYNCIN1
SYNCIN2
HOLD
CLPIN
DIVOUT
1/2C LK
XPOWERSAVE
RA[7..0]
RB[7..0]
GA[7..0]
GB[7..0]
BA[7..0]
BB[7..0]
AIN
BIN
CIN
RT
RB
3.27V
1.17V
AO[8..1]
BO[8..1]
CO[8..1]
EXTCLP
CLK
-OE
FIN-A
FIN-B
PFDINH
VCOOUT
V1
Sync&
Clock
Sel
IC421
74LCX157
1B
2B
4B
1A
2A
4A
-A /+B
1Y
2Y
4Y
13,1
4
9,10
5,6
SUB _Y
SUB_ Cb
SUB_ Cr
SUB_ HD
2
1
SUB _VD
About 60MHz
CN10
19
18
21
CD_ HD
CD _VD
CD_CLK
SEL _CD
16
12pin TO CONNECTOR PWB
5
6
THERMO
BSREQ
11
PXOE
CAR D_RST
C 30..23
Y 39..32
SDRAM
512Kx128bitx4 BANK
8
V0_HSYNC
V0_VSYNC
V0_CSYNC
OV0_V
V0_HSYNR
OV0_HSYNR
V0_PDEN
OV0_PDEN
V0_CLP
OV0_CLP
V0_HSYNC2
V0_VDCLK_I
OV0_HSC2
OVCLK(Max60MHz)
V0_RA[7..0]
V0_RB[7..0]
V0_GA[7..0]
V0_GB[7..0]
V0_BA[7..0]
V0_BB[7..0]
8
8
8
8
8
XPW R_SV
V1_GA[7..0]
V1_BA[7..0]
V1_RA[7..0]
8
8
8
OV1_VCKO
( = 15M
.
.
Hz)
V1_VDCLK_O
OV1_CLP
V1_CLP
SAD C_OE
V1_HSYNR
V1_HSYNF
V1_PDEN
OV1_HSNR
OV1_HSNF
OV1_PDEN
V1_HSYNC
V1_VSYNC
V1_VDCLK_I
OV1 _H
OV1_V
OV1_VCLK
SDRAM BUS
D:128,A:11,BA:2,Ctrl:13
SDCLK=100MHz
DO_RA[9..2]
DO_GA[9..2]
DO_BA[9..2]
DO_HSYNC
DO_VSYNC
DO_HDISP
DCLKMCK_REF
LCLK
BINT
BCLK
XBCS
BWAIT
XRESET
PLL_S
BD,BA
ACL_S IG
12
CLR_ SW
12
14
RXD 1_T
TXD 1_T
FPC 30pin TO MAIN PWB
FPC 40pin (TO PC CARD UNIT)
MOUNTED ON CE10 ONLY I2C=CH4, SERIAL=CH1
CXA3506R
VCO
WHISKER
CORRECTIO
N CIRCUIT
IC423, IC424
VIDEO SIGNAL
PEAK DETECTION
V1 ADC
RT, RB SETTING
CIRCUIT
IC319-322
HY57V653220BTC-7 4 PCS.
3.1.5 PC I/F BLOCK DIAGRAM