Quectel BG950A-GL - Page 46

LPWA Module Series
BG950A-GL&BG951A-GL_Hardware_Design
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Table 15: Pin Definition of CLI UART Interface
Table 16: Pin Definition of Debug UART Interface
Table 17: Pin Definition of CLI/GNSS UART Interface
AT+IPR can be used to set the baud rate of the main UART interface, and AT+IFC can be used to set the
hardware flow control (the function is disabled by default). See document [3] for more details about these
AT commands.
The module provides 1.8 V UART interfaces. A voltage-level translator should be used if your
application is equipped with a 3.3 V UART interface. It is recommended to use a level-shifting chip
without internal pull-up. The voltage-level translator TXB0108PWR provided by Texas Instruments is
recommended.
The following figure shows a reference design of the main UART interface:
Pin Name
Pin No.
I/O
Description
Comment
CLI_TXD
95
DO
CLI UART transmit
1.8 V power domain
If these pins are unused, keep
them open.
CLI_RXD
94
DI
CLI UART receive
Pin Name
Pin No.
I/O
Description
Comment
DBG_TXD
23
DO
Debug UART transmit
1.8 V power domain
If these pins are unused, keep
them open.
DBG_RXD
22
DI
Debug UART receive
Pin Name
Pin No.
I/O
Description
Comment
CLI/GNSS_TXD
27
DO
CLI/GNSS UART transmit
1.8 V power domain
If these pins are unused, keep
them open.
CLI/GNSS_RXD
28
DI
CLI/GNSS UART receive
NOTE