Instruction Reference Manual 47
Description
• LD (mn),A: Loads the memory location whose address is mn withthedataintheAccumula-
tor.
• LD (mn),HL: Loads the memory location whose address is mn withthedatainregisterL,
then loads the memory location whose address is 1 plus mn with the data in register H.
• LD (mn),IX: Loads the memory location whose address is mn with the low order byte of the
data in index register IX, and the memory location whose address is 1 plus mn with the high
order byte of the data in IX.
• LD (mn),IY: Loads the memory location whose address is mn with the low order byte of the
data in index register IY, the memory location whose address is 1 plus mn with the high order
byte of the data in IY into.
• LD (mn),ss: Loads the memory location whose address is mn with the low order byte of the
data in word register ss (any of the word registers BC, DE, HL or SP). Then, loads the memory
location whose address is 1 plus mn with the high order byte of the data in word register ss.
LD (mn),A
LD (mn),HL
LD (mn),IX
LD (mn),IY
LD (mn),ss
Opcode Instruction Clocks Operation
32 nm LD (mn),A a (mn)=A
22 nm LD (mn),HL b (mn)=L;(mn +1)=H
DD 22 nm LD (mn),IX c (mn)=IX
(low)
;(mn +1)=IX
(high)
FD 22 nm LD (mn),IY c (mn)=IY
(low)
;(mn +1)=IY
(high)
——
ED 43 nm
ED 53 nm
ED 63 nm
ED 73 nm
LD (mn),ss
LD (mn),BC
LD (mn),DE
LD (mn),HL
LD (mn),SP
c
c
c
c
c
(mn)=ss
(low)
;(mn +1)=ss
(high)
(mn)=C;(mn +1)=B
(mn)=E;(mn +1)=D
(mn)=L;(mn +1)=H
(mn)=P;(mn +1)=S
Clocking: (a)10 (2,2,2,1,3) (b)13 (2,2,2,1,3,3) (c)15 (2,2,2,2,1,3,3)
Flags ALTD I/O
S Z L/V C F R SP S D
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