Radio Shack Quick Printer II Reference Handbook

Now, look at Fig~re 3 and you'll see that bits
A12, A13 and A14 are connected to Z21, a
dual, 2-input to 4-line decoder/demultiplexer.
The C1 and C2 inputs are connected in such a
way as to make Z21 into a 3-input to 8-line
decoder. The G1 and G2 inputs to Z21 are chip
enables. As shown, when these inputs are at a
logical
0, Z21 is active. When high, Z21 is dis-
abled and none of its eight outputs are low. The
G-enables are controlled by OR gate Z73, pins
4, 5 and 6. Pin 4 is tied to A 15, the most signifi-
cant bit of the address bus.
Notice in the memory map breakdown that A 15
is always low when addressing the various mem-
ories.
Z73, pin 5, is tied to RAS* (Row Address
Select). Go
back to the large Schematic, Sheet 1,
and find MREQ at pin 19 of the CPU. As statec!
earlier, MREQ only goes low when the CPU
needs
or wants to output memory data. Follow
pin
19 down to Z72, pin 4. This buffer sources
RAS*
and it is the same signal as MREQ.
Back
to Figure 3. When A 15 and RAS* are low
at the same time, a low will be outputted by
Z73, pin 6. This low will enable Z21. When Z21
turns on, one of its outputs will go low, depend-
ing on
the status of A 12, A 13 and A14. For
example, if these three inputs are at logical zero,
pin 9 will go low. If
all three inputs are high, pin
4 will go low. You
might consider A12 through
A 14 as supplying an octal address to Z21. Since
there are eight states in an octal code, then there
could be one of eight lines selected (Output 0
through Output 7).
We can sum up Z21's function quite simply: It
decodes the most significant digit of the hex
address. Using Z21
and the last two bits, A 11
and A 10, we can define anyone of the four
"memories" available to the CPU in LevelL
Address Decoder Programming
Attached to the outputs of Z21 is Z3, which is
called a "DIP" shunt. A DIP shunt is like a
shorting bar array, except that the bars may be
broken. By breaking some bars and leaving the
others intact, the address decoder is programm-
ed
to reflect the amount of RAM or ROM the
CPU has available for use. In Figure 3, "Address
Decoder", 23 is shown with two broken short-
ing bars.
We will use this configuration in our
discussions.
ROM Decoding
When the CPU needs instructions on how to
perform a certain task, it must access ROM.
ROM Decoding
is performed as follows: The
CPU needs a memory, so RAS* will go low. The
address for ROM starts with hex 0, so A 15, A 14,
A 13 and A 12 go low. Z21 becomes active, due
to the low at A 15 and RAS*. Pin 9 of 221
goes low. Follow pin 9 through the shorted bar
at 23, pins 10 and 7, past the pull-up resistor
R61
and out to ROMA*. If you find ROMA* on
the large Schematic, you'll see it goes to ROM
A, (233, pin 20.) This pin is the CS (Chip
Select)
and it is active low (as the inverting circle
on pin 20 shows). Z33 turns on, which means
that its output becomes active (Note: The
ROM's outputs are tri-stateable like the buffers.
When CS goes low,
the ROM outputs will switch
from a high
impedance or off-state to an on-
state. When on, the outputs will go low or high
depending on the data in the ROM at the
address specified.)
We got the address applied to ROM A and we
got ROMA* to go low, so ROM A is turned on.
But now we need to insure a data path is opened
so that we can pass data from ROM to CPU.
Notice
in Figure 3, ROMA* is also attached to
pin 9 of NAND gate 274. A low on pin 9 will
cause a resulting high
at pin 8. Z74, pin 8, is
tied to 273, pin 9. 273, pin 8 passes a high to
274, pi~ 5. Z74, pin 4, is tied to RD*, part of
the CPU control group. Since the CPU is trying
to read data from ROMs, RD* will be low. Pin
4
of Z74 will then be high, because RD* is in-
verted by Z52, pins 13 and 12.
OK, we know pins 4 and 5 of Z74 are high, so
that makes pin 6 low. This low is MEM*. If you
21

Radio Shack Quick Printer II Specifications

General

Brand	Radio Shack
Model	Quick Printer II
Category	Desktop
Language	English