Radio Shack Quick Printer II Reference Handbook

Divider Chain
Upon the next negative excursion of the clock
pulse, outputs would look as follows:
The Divider Chain
circuit (Z65, Z50, Z12 and
Z32) consists of four-bit ripple counters. They
hve a maximum count of 16, but external cir-
cuitry may modify this maximum.
Figure 6 shows a simplified block diagram of the
counter chain. Refer to Figure 6 and to Sheet 2
during our discussion of the counter chain.
Output A
Output B
Output C
Output 0
o
1
1
1
The
next counter in the chain is Z50. The input
is on pin 14 and the divided frequency is at pin
11. This device is externally modified to divide
the
input frequency by 14. Z50 counts up
normally to a binary value of 13. Thus the
counter's
outputs are as follows:
Z65 is a binary counter that is split into two
parts. The chain input from the conditioning
logic is applied to pin 1 of Z65. The Band C
outputs are used for Video RAM addressing, and
the
output of Z65 at pin 8 is applied to the next
counter in the chain. This part of Z65 divides
the chain frequency
by 4. Since the chain is
887.0461 kHz, the output of Z65, pin 8, is
221.760 kHz. The other part of Z65 will be used
later.
Pin
12
Pin 9
Pin 8
Pin
11
(Output A)
(Output B)
(Output C)
(Output D)
1
o
1
1
which is equal to 14. But notice AND gate Z66,
pins 3, 4 and 5. These pins are tied to outputs
B, C and D. The output of the AND gate's pin
6 will go high and clear Z50 back to zero. This
clear pulse
is extremely rapid - about 50 nano-
seconds! The binary
count of 14 would there-
fore
be almost invisible to a standard oscillo-
scope and
so would the clear pulse to pins 2 and
3. The time that Z50 is actually reading binary
14 is so short that we can ignore it. Therefore,
Z5£) will count from 0 to 13 and will then reset
back
to 0. Since 221.760 kHz is put into Z50,
the output at pin 11 will be 15.840 kHz. This
frequency
will be used by the sync generator
circuits
to produce horizontal sync.
The
next divider is Z12. It is wired to perform a
division
by 12. It counts up normally until the
outputs enable AND gate Z66, pins 9, 10 and
11. This happens at the twelfth falling edge of
the clock. Z66, pin 8, will then go high and clear
Z12 back to zero. Once again, this clear pulse
wou
Id be very hard to observe using an oscillo-
scope. Thus we
can ignore this count and con-
HORIZ
•
CHAIN
INPUT
887.0416kHz
31
~
PART OF
P,
Z65 Z50 Z12
8
14
11 14
11
14
~4
221.760kHz
~14
15.840kHz
~12
1.320kHz
'------
FIGURE 6. Divider Chain Block Diagram

Radio Shack Quick Printer II Specifications

General

Brand	Radio Shack
Model	Quick Printer II
Category	Desktop
Language	English