Alphanumeric/Graphic
Shift
Register
Z10
is
the
Alphanumeric
Shift
Register
and
Z11
is
the
Graphic
Shift
Register. Both devices
receive parallel
data
from
their
respective genera-
tors.
The
parallel
dot
data
is
loaded
into
the
registers
and
the
dot
clock
(labeled SH IFT) will
march
the
dots
out,
one
behind
the
other,
to
the
video mixer.
We
will discuss
the
Alphanumeric
Shift
Register first.
There
are a few restrictions
when
the
Alphanu-
meric
Shift
Register
should
serialize
dot
data
and
when
it
shouldn't.
First,
the
data
must
be
alphanumeric
and
not
graphic.
Second,
the
elec-
tron
beam
must
be
on
one
of
the
seven scan
lines
that
are reserved
for
dot
data
and
not
on
one
of
the
five lines
that
are blanked (held off)
between
character
lines.
Third,
the
electron
beam
must
be
on
one
of
the
192
scan lines
that
define
the
video
portion
of
the
screen.
(Not
in
boundary
space:
upper,
lower, left
or
right.)
Once
all
three
restrictions are
met,
the
dot
data
is
parallel-loaded
into
the
Register. NAN D gate
Z26
insures all
conditions
are
met
before
data
is
stored
in
Z10.
Delay
bit
7*
is
sourced
from
latch
Z27,
pin 2,
and applied
to
pin
10
of
Z26.
When
this
input
is
high,
data
in
Z63
is
low, which defines an alpha-
numeric
character.
Delay L8
is
sourced
at
Z27,
pin
11,
and
is
con-
nected
to
Z26,
pin 12. When
this
input
is
high,
the
beam
is
scanning
in
a
character
line
and
not
between
character
lines.
Delay blank
is
sourced
at
pin 7
of
latch
Z27
and
is
tied
to
pin 9
of
Z26. When
this
input
is
high,
the
electron
beam
is
in
the
video
portion
of
the
screen
and
is
not
located
near a
sync
pu
Ise
or
in
some
boundary
region.
All
three
restrictions have
then
been met. Pin
13
of
Z26
is
tied
to
the
inverted
LA
TC H signal.
When pin
13
of
Z26
goes high,
the
dot
load
process will be activated
by
a low
on
Z26, pin 8.
38
Upon
the
next
clock
pulse
at
pin 7
of
Z10,
dot
data
will be loaded
into
the
shift
register.
After
LATCH goes back high (one
dot
time
after
going
10wL
the
Shift
Register
starts
clocking
dot
data
out
at
pin
13
in
a serial stream (when LATCH
goes high, pin
13
of
Z26
goes low causing pin 8
to
go high). Each
time
LATCH goes high, it
forces ASCII
and
conditional
data
to
be
stored
in
Z27
and
Z28.
During
this
time,
Z10
will
not
be shifting
dots
out
at
pin 13.
Z10
only
shifts
data
out
when pin
15
is
high. When low,
pin
15
forces Z10
to
load
data
from
the
Charac-
ter
Generator.
Notice
the
unused
inputs
to
Z10. Pin 9,
the
clear
input,
is
pulled
up,
via R40,
to
Vce.
When
this
pin
is
low (due
to
a
short),
you
would
have a
blank
screen. Pins
14,
3,
2, 1
and
6 are
tied
to
ground.
Pin
14
gives
you
that
blank
dot
between
adjacent
characters. Pins 2
and
3 are
not
used,
but
are register
inputs
like pin 4
or
5. Pin 1
is
for
serial
data
input
and
pin 6 inhibits
the
clock
input.
They
are
not
necessary
in
this
application.
The
Graphics
Shift
Register
is
Z11.
Operation
is
almost
the
same as
Z10,
except
for
the
condi-
tion
that
must
be
met
for use.
The
graphics con-
ditions
are as follows: First,
Z63
must
specify a
graphics
character
instead
of
an
alphanumeric
character.
Second.
the
electron
beam
must
be
in
the
video region
of
the
screen.
There
are
only
two
conditions
restricting graphics. Since a
character
rectangle
ends
where
another
starts,
there
is
no
inter-character line blanking. If
you
turn
on
all
of
the
graphic cells,
you
would
have a full, large
square
with
no
holes
and
boun-
daries
surrounding
the
square.
Once
all
of
the
restrictions are
met,
graphic
dot
data
may
be
loaded
into
Z11
for
shifting
to
the
video mixer.
The
other
NAN D gate
in
Z26
is
used as
the
graphics load enable.
The
inverse
of
delay
bit
7*
(D
LY
bit
7)
is
sourced
at
Z27,
pin
3.
It
is
applied
to
Z26. pin
4. When high,
this
input
tells
Z26
that
Z63
does
indeed
contain
a
1/1"
which defines a graphic
code.
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