Delay blank (DLY BLANK)
is
tied
to
Z26, pins
1 and 2. When high,
this
input
tells
Z26
that
the
electron beam
is
indeed in
the
video
portion
of
the
screen.
Once
all
conditions
are
met
and LATCH goes
low,
Z26
will go low.
Just
like Z10, Z11 will
load
dot
data;
and when pin
15
goes
back
high,
the
shift
process will
start.
The
six graphic
dots
are shifted
out
of
pin 13.
Notice pin 9
of
Z11
is
pulled
up
by R40. Like-
wise, pins
3,
2, 1 and 6 are tied
to
ground. But
pin
14
is
used this time. In graphics,
there
is
not
a blank
dot
space between
character
rectangles.
Sync
Generator
The
Sync
Generator
circuit
accepts timing sig-
nals from
the
Divider Chain
to
develop horizon-
tal and vertical sync pulses for
the
display. These
pulses are used by
the
display
to
control
the
CRT's
electron beam.
The
sync pulses are generated by logic which
operate
like linear elements.
26,
a CMOS inverter,
is
used
to
generate
the
horizontal pulse; and
Z57
is
used
to
generate
the
vertical pulse.
The
HDRV (Horizontal Drive) sig-
nal
is
sourced from
the
Divider Chain
at
Z50, pin
11. This signal
is
buffered by Z6, pins
13,
12, 1
and
2,
and
applied
to
potentiometer
R20. R20 '
controls
where
the
horizontal pulse starts
in
reference
to
HDRV. When R20's wiper
is
close
to
Z6, pin 2,
the
horizontal pulse will
start
almost
at
the
same
time
as HDRV goes high.
When
the
wiper
is
moved
in
the
opposite
direc-
tion,
there
is
a delay between
the
time
HDRV
goes high and
the
time
the
horizontal pulse
starts.
R20
is
not
performing
this
phase
shift by
itself. C20,
together
with
two
inverters
in
26,
form
the
complete
shift network.
Here's
how
it works: HDRV goes high, causing
Z6, pin 2
to
go
high (in
this
case
about
5.0
volts). A
current
flows
through
R20 charging
C20. While C20 charges,
the
voltage
at
pin 3
of
Z6 slowly increases from zero as
the
current
through
R20 decreases.
After
a length
of
time,
the
voltage
at
pin 3
of
Z6 will be high enough
for
pin 3
to
"see"
a high. Z6, pin 4 goes low,
causing pin 6
to
go high. C20 rapidly charges.
Everything stays
in
this
mode
until HDRV goes
low.
At
this
point,
C20 starts
to
discharge
at
the
same rate
it
charged. When
the
voltage
at
Z6, pin
3 decreases
to
a logical
"0"
level, pin 4 will go
high, causing pin 6
to
go low. C20 rapidly dis-
charges.
The
process cycle
is
now
complete
l:Jntii
the
next
time
HDRV goes high.
The
time
the
voltage level
at
pin 3
of
Z6 stays above
the
minimum logical
"1"
level determines
the
amount
of
shift
from HDRV.
The
effect
of
R20's position (which adjusts
the
delay time) on
the
screen
is
a horizontal
shift
of
the
video dis-
play.
After
the
horizontal signal
is
phase shifted,
the
horizontal pulse
must
be shaped. C21 and R43
form a differentiation
network
which creates a
smaller pulse
of
known
width from
the
shifted
HDRV signal.
Operation
is
quite
simple. When
Z6, pin 6 goes high, C21 and R43 differentiate
the
rising edge. A
narrow
pulse
is
passed
to
Z6,
pin 11, inverted
by
pin
10
and inverted and buf-
fered by Z6, pins 9 and
8.
The
net
result
is
a
pulse
about
four
microseconds long, called hori-
zontal sync.
The
vertical sync phase shift operates
in
the
exact
same
manner
as
the
horizontal. Z57
is
used
as.
the
active element, for which
R21
and
C26 form
the
delay network.
The
differential
network
consists
of
C27 and R44. Notice
the
only difference between horizontal and vertical
circuits
is
the
value
of
the
two
capacitors.
39
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