RCA Spectra 70 - Page 28

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Interrupt Status Registers

(Cont'd)

Program Interrupt

Bit

Positions 3 through 5

are

not

used

and

must

be zeros.

Bit

Positions 6

a,nd

7 contain

the

program

indicators. When

an

inter-

rupt

occurs due to a

parity

error

in Main Memory

or

Scratch

Pad

Memory,

the

program

indicators

are

stored

in

this

field

in

P 4

as

given in

table

6.

Table

6.

Program Indicator Codes

Program

Indicators

Definition

00

Neither

error

has

occurred.

01

Scratch

Pad

Memory

parity

error

has

occurred.

10

Main

Memory

parity

error

has

occurred.

11

Scratch

Pad

Memory

parity

error

and

Main

Memory

parity

error

have

occurred.

Bit

Positions 8 through

11

contain

the

memory

protection key.

This

field is

set

by

the

program

to indicate

the

desired

prot~ction

key.

When

an

interrupt

occurs

or

a

Program

Control

instruction

is executed,

the

memory

protection key is

extracted

from

this

field

of

the

processor

state

being

initiated

and

placed

in

a machine

register

where

it

performs

the

memory

protect

function.

The

four-bit

key provides a possible 15 keys

ranging

from

(lL6

to

(F)

16'

Each

2,048-byte block

of

main

memory

has

its

individual

machine

register

for

the

protection key. When

the

key

related

to

the

cur-

rent

processor

state

and

the

key

related

to

the

main

memory

block

are

equal,

or

either

is zero,

the

main

memory block accepts a

data

store.

Conversely,

if

the

keys

do

not

match,

and

neither

is zero,

an

address

error

(protection)

interrupt

occurs.

No-tes:

1.

If

the

memory

protect

feature

is

not

installed,

this

field

must

be zero.

2.

Keys

are

effective on actual

(after

translation)

addresses.

Bit

Position

12

designates

the

internal

decimal code.

When

an

inter-

rupt

occurs

or

a

Program

Control

instruction

is executed,

the

decimal code

(either

USASCII

or

EBCDIC)

for

the

processor

state

being

initiated

is

established by

the

setting

of

this'

bit.

If

the

bit

is 1,

USASCII

Code is

established;

if

the

bit

is 0,

EBCDIC

is established.

Note: The

setting

of

this

Decimal Code does

not

affect

any

automatic

trans-

lation

of

data

read

into

or

written

from

the

processor.

The

Decimal

Code is used to determine

what

zone configuration

(USASCII

or

EBCDIC)

is to be established

internally

when

executing

the

deci-

mal

arithmetic

instruction

set,

the

Edit

instruction,

and

the

Edit

and

Mark

instruction.

Bit

Position

13

is defined

as

the

70/45-46 Mode Control

bit

(T-bit)

for

the

70/46

processor.

It

specifies

whether

translation

is allowed.

Notes:

T =

1:

70/46 Mode: Direct

Addressing

or

Translate

Addressing

is specified by

the

setting

of

the

D-bit.

T

=

0:

70/45 Mode:

Direct

Addressing

only,

the

setting

of

the

D-bit is ignored.

1. General

reset

resets

the

T -bit to zero.

19

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