Block 8
Block 9
Block
10
Block 11
Block
12
Program
Interrupt
•
If
the
program
test
bit
is set, control is transferreQ. to
the
state
speci-
fied by
the
Program
Control
instruction
(directly
or
indirectly - see
Pro-
gram
Control
instruction).
•
The
condition code
setting
and
the
program
mask
are
extracted
from
the
P
counter
of
the
initiated
state
and
stored in
the
appropriate
registers.
• The memory protection key,
the
decimal
code}
and
the
privileged mode
bits
are
extracted
from
the
Interrupt
Status
register
of
the
initiated
state
and
stored
in
the
appropriate
registers.
•
The
program
test
flag
hit
(2
31
)
in
the
Interrupt
Flag
register
is set.
•
The
instruction
at
the
address
specified in
the
P
counter
of
the
initi-
ated
state
is staticized
and
executed.
Notes:
1. When a
Program
Control
instruction
has,
the
program
test
bit
set,
the
first
instruction
of
the
initiated
state
is always executed before
any
interrupt
is taken.
2.
If
the
initiated
state
permits
the
program
test
interrupt
(via
the
Interrupt
Mask
register),
a
program
test
interrupt
occurs
after
the
first
instruction
in
the
initiated
state
is executed.
3.
An
interrupt
condition can occur while executing
the
first
instruc-
tion
of
the
initiated
state.
If
it
does,
and
is permitted,
it
is serviced
before
the
program
test
interrupt.
General Notes for Program
Interrupt:
1.
The
decimal mode
in
the
70/46
Processor
is
either
USASCII
or
EBCDIC
as
specified by
bit
12
in
the
Interrupt
Status
register.
When
an
automatic
interrupt
occurs
or
a
Program
Control
instruction
is
executed,
the
decimal mode is
not
stored
in
the
Interrupt
Status
register
of
the
terminated
state. The mode
of
the
state
being
initiated
is determined by
the
mode
bit
in
its
own
Interrupt
Status
register.
Consequently, to change mode,
the
mode
bit
of
the
Interrupt
Status
register
associated
with
the
appropriate
state
must
be
altered
by
the
program,
and
that
state
must
be initiated
either
by
an
inter-
rupt
condition
or
a
Program
Control instruction. This is
the
method
available
to
the
program
for
changing
the
mode.
2.
The
interrupt
flags
are
scanned to
determine
whether
or
not
an
interrupt
shall occur
if
the
Interrupt
Mask
register
associated
with
the
current
state
or
the
Interrupt
Flag
register
is
written
into
by
the
program.
3.
Changing
the
protection key, decimal mode,
or
privileged mode
fields in
the
Interrupt
Status
register
does
not
change
the
protec-
tion key, machine mode,
or
privileged mode bits
of
the
associated
processor state. To change
the
status
of
the
processor,
the
state
concerned
must
be
initiated
by
an
interrupt
condition
or
a
Program
Control instruction.
4.
The condition
of
General
register
15
of
states
P 3
and
P
4,
at
time
of
interrupt,
and
loading of
the
weight is
as
follows: The low-order
16 bits
are
cleared. The least significant 7
bits
are
loaded
with
the
weight.
The
next
most
significant 9 bits are
zeros.
The
high-order
16 bits
are
not
cleared,
but
are
shifted
one
bit
to
the
left.
35
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