LIST
OF
TABLES
LIST
OF
ILLUSTRA
liONS
CONTENTS
(Cont'd)
Page
Table
1.
Basic Hexadecimal
Marking
System
..................
3
Table
2.
Use
of
General
Registers.
. . . . . . . . . . . . . . . . . . . . . . . . . . .
11
Table
2A.
Analysis of Model 70/46 Move
Instruction
Results
...
15
Table 2B. Analysis
of
Overlapped
and
Non-Overlapped
Fields
of
Model 70/46 Move
Instruction.
. . . . . . . . . . . . . . . . . . . . . 15
Table 3. Processor
State
Registers
...........................
17
Table
4.
Instruction
Length
Codes
...........................
17
Table
5.
Interrupt
State
Identifier Codes . . . . . . . . . . . . . . . . . . . . . . 18
Table
6.
Program
Indicator
Codes
...........................
19
Table
7.
Register
Addressing
in
Processor
States
. . . . . . . . . . . . . . .
21
Table
8.
Interrupt
Conditions
and
Priority
...................
22
Table
9.
Interrupt
Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 10. Command
Code Operations
.........................
.
41
Table 11.
Input/Output
Channel Registers
.....................
45
Figure
1.
Data
Formats
...................................
.
Figure
2.
70/46
Translation
Flow
...........................
.
Figure
3. Functional Logic
of
Automatic
Interrupt
...........
.
Figure
4.
Functional Logic
of
Program
Control
Instruction
...
.
Figure
5.
Functional Logic
of
Start
Device
Instruction
........
.
Figure
6.
Functional Logic
of
Halt
Device
Instruction
........
.
Figure
7.
Functional Logic of
Test
Device
Instruction
........
.
Figure
8.
Functional Logic
of
Check Channel
Instruction
......
.
Figure
9.
Functional Logic
of
Servicing a
Data
Transfer
......
.
Figure
10. Functional Logic
of
End
and
Chaining
Servicing
....
.
Figure
11. Functional Logic
of
Interrupt
Servicing
...........
.
Figure
12. Dual-Processor Complex
...........................
.
Figure
13.
Master/Satellite
Complex
..........................
.
Figure
14. Maximum Multi-Processor Complex
................
.
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