Block 9
Block
10
Block 11
Input/Output
Operation
• A
test
is made to see
if
the device is on
the
multiplexor channel.
If
it
is,
the
subchannel registers
are
sent back to non-addressable main memory.
In
either
case,
program
control continues
with
the next instruction
or
with
the
instruction
that
was
interrupted
due to chaining
and/or
end servicing.
Note:
If
the operation
that
was
terminated
was a
burst
mode operation,
the
burst
mode is completed
at
this point
and
other
multiplex mode
operations can be directed to devices on
the
multiplexor channel.
The processor does
not have
to
wait
for
the
burst
mode
terminating
interrupt
to occur.
•
Entry
to this block occurs when command chaining is to
take
place.
The
standard
device byte is tested to see
if
the
status
modifier
bit
is set.
If
it
is,
the
next
Channel Command Word (CCW) address is incremented
by eight. (The next channel command word
in
sequence is skipped.)
•
In
addition
to
continuing command chaining processing,
entry
to
this
block occurs
from
Servicing a
Data
Transfer
when
the
following conditions
are
present:
a. The byte count is equal to zero.
b.
The Chain
Data
(CD) flag is set.
The next Channel Command Word
(CCW) is fetched
from
main
memory
and
placed in
the
appropriate
channel registers. The next Channel Com-
mand
Word address is incremented by eight.
Block
12
• A
test
is made to see
if
the
next
command in sequence is a
Transfer
in
Channel command.
Block
13
•
If
the
command is not a
Transfer
in
Channel command, a
test
is made
to see
if
this is a command chain
or
a
data
chain operation.
If
it
is a com-
mand chain operation,
the
new command is sent to
the
specified device con-
trol electronics. (This is not required
if
this
is a
data
chain operation.)
Block 14 • A
test
is made
to
see
if
the chaining servicing
has
occurred
for
a device
on
the
multiplexor channel.
If
it
has, a
test
is made to see
if
it
is a
burst
mode operation.
If
it
is not a
burst
mode operation,
the
subchannel regis-
ters
are
sent
back to non-addressable main memory.
In
all cases,
program
control continues
with
the
next instruction,
or
with
the
instruction
that
was
interrupted
due to the chaining servicing.
Block
15
•
If
the
next command in sequence is a
Transfer
in Channel command,
the main memory address specified
by
the
Transfer
in
Channel command
is tested to see
if
it
is on a double word boundary.
Block
16
•
If
the
main memory address specified
in
the
Transfer
in Channel com-
mand
is on a double word boundary,
this
address is placed in
the
next
Channel Command Word address
and
control is
transferred
to Block
11
which fetches
the
CCW specified by the
Transfer
in Channel command.
Block
17
•
If
the
main memory address specified
in
the
Transfer
in
Channel com-
mand
is not on a double word boundary,
the
program
check
bit
is
set
in
the
channel
status
byte.
76
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