Renesas RH850/U2A 292pin - Page 9

RH850/U2A 292pin 1. Overview
R20UT4545ED0102 Rev.1.02 Page 9 of 58
May 27, 2021
Following figures provide the drawing of top and bottom views of the piggyback board.
R22
R7
R34
R23
R6
C12
R143
Figure 1.4 PiggyBack Board bottom view
RH850- U2A- 292PI N- PB- T1- V1
Not Connect ed
12
3. 3V
5V
CN17
CN6
RHSI F/ MSPI
1
5V
13
9
11
U2A16
LED
5 V
SW ON
SVR
GND
2
0
12
5 V
GND
CN11
Reset
10
4
0
5
AP0 _
Emul at or I nt er f ace
5. 0V
U2A8
VCC
9
SYSVCC
VDDI OF
13
GND
8
6
GND
10
12
11
14
15
5 V
2
3
2
5V
3 . 3 V
12
15
R20
13
15
E2 VCC
LVDVCC
FL MD0
SVRAVCC
LED14
60
P4 _
C27
2
14
I C2 - MDI O
1
0
5
AP4_
CN12
A0VREFH
6
I C2- 41
I C2- 42
I C2 - RESETN
JP11
D016636_06_V01
10
I C2- RXD2
JP20
FI L1
CN13
XTAL1
CN14
CN15
CN16
FLMD2
4
CN10
CN11
P5_
JP10
3 . 3 V
JP39
0
CN20
14
JP40
8
JP38
JP35
14
JP15
JP13
FL MD1
A2VCC
12
8
1
VMONOUT
5V
13
E0 VCC
4
0
9
1
4
0
8
6
3
10
1
5 V
P3_2
4
Reset
85 59
24
15
103
RB1- RB4
VDD
P3_3
GND
VDD
8
A0VCC
4
7
A1VCC
P2 4 _
REG
6
11
9
7
9
7
5
CN4
VDD
VDDS
PULL_UP_PI N1- 9
PULL_UP_PI N11- 19
LED13
5
5. 0V
LED1
PULL_DOWN
JP14
6
9
C6 1
1
3 . 3 V
P2 4 _
13
3
JP37
14
AP0 _
7
AP0 _
12
6
AP1 _
P10_ P17_ AP2_
X1
AP2_12
AP3_AP2_P21_ P17_
3
JP41
VDDS
3
P10_
AWOVCL
P2 1 _
ERROROUT
X2
P2 2 _
P2 0 _
P2 2 _
P2 0 _
I C2 - MDC
A5. 0V
E1 VCC
2
C6 0
10
8
P2 1 _
3. 3V
P2 0 _
PWRCTL
VMONOUT
RESET
GETH0 VCL
TRST
FLMD0
1
JP0_
JP0_
5
AP4_
3 . 3 V
3 . 3 V
4
2
JP4
2
3. 3V
R83
JP18
JP17
P2 _
Ba r c ode
LED10
JP19
3. 3V
3
3. 3V
TP10
JP30
AP2_
4
P5_
0
0
8
7
11
1
JP31
0
2
7
0
10
2
6
GND
4
8
P2 _
LED15
7
1
6
2
P3_
3. 3V
5
3
13
1
5
11
15
5 9
12
3
3
JP36
3
P3_
MODE0
0
LED11
PWRCTL
6
ERROROUT
LED12
13
CN7
8
4
220
144
3
1
P4_
TP8
TP6
TP5
RB4 RB2
RB3
RB1
TP7
X1
I C2
VA2
VA1
FC1
I C1
CN9
CN8
TP4
TP9
C24
C25
C26
JP1
JP9
JP8JP6
JP2
2
CN5
JP33
JP23
P6_
1
A3. 3V
9
P6_
11
P4 _
2
Made i n Eur ope
3 2
6
JP22
4
RoHS- compl i ant
JP25
0
R24
5
GND
JP32
R84
JP34
JP16
3
2
JP12
JP7
SVRDRVCC
7
A2VREFH
5
0
A1VREFH
7151114136427
1
R25
JP3
SW1
JP5
1
19
10
1
Figure 1.3 PiggyBack Board top view