mnruiDjiMM HEMOX B225 SECTION 3/7
3.5.1 Digital signal processing
The HF signal is converted in IC13 (SAA 7010} into
diqital siqnals and split into audio and information
data (subcode, for the slave
processor).
The CLOCK
signal is also regenerated in JC13. The audio data
are brought into the correct time slot pattern. Corrupted
audio data are not recognized in 1C12 and corrected
if necessary. Should the errors be incorrigible, the
missing sample values are replaced in. IC10 (SAA 7000)
through interpolation. Should this also be infeasible,
the HF signal is slowly muted (soft
muting).
The speed
of the CD motor is controlled by the signal MCES (IC1,
pin
4 )
.
3.5.2 Digital sine-wave generator
The PROM (IC4) contains a value table for the sine-wave
signal which represents the maximum possible level
of a CD.
The circuit consists of IC5 through IC9 with IC5 and
IC6 supplying the addresses for the PROM. Parallel/serial
data conversion is performed in IC3. The change-over
between audio data from the CD and the 1 kHz sine-wave
signal is controlled by IC1.
3
•
5
•
3
HFL and DO detector
The HF signal is fed into the inverting differential
amplifier Ql and Q2 through C6 and R2. The output signals
are DC-decoupled via C8 and C9 respectively and tied
to DC ground via D2 and D3. D4 and D5 or D6 and D7
respectively constitute a full-wave rectifier each
through which the capacitors C10 or Cll are charged.
With a normal HF signal the DO signal is "L
Si
and the
HFL signal is "H". If the HF signal drops to approxi-
mately 70% of the normal value, the HFL signal also
changes to
!,
L
t!
.
Only when the HF signal drops to
approximately 10% of
-
the normal value does the DO signal
change to "H".
To prevent the output signals of IC11 from being
influenced too strongly by minor contaminations (e.g.
fingerprints) on the CD, transistor Q3 has been added to
the output. When the RF level is at nominal value, pin 7
of IC11 is
"H
l!
.
Q3 becomes conductive and the circuit
with Cll receives a smaller time constant. With level
fluctuations caused by minor contaminations, the levels
of the two input capacitors fluctuate in parallel, but
neither the DO nor the HFL signal are affected.
3.6 DAC PCS
1.769.280
.
Tfee"
following'circuits are implemented on this PCB:
- Digital filtering (oversampling) and digital/analog
- •conversion
- Level adjustment and headphones" aTifffiifier
3.6.1 Digital filtering (oversampling) and D/A conversion
IC1 (SAA 7030) contains two identical filters for both
channels. These filters feature 3 sections:
~ Oversampling section
- Transversal digital filter
- Noise shaper
After each scanning cycle, the new sample values are
inserted by interpolation into the 16-bit information
arriving from the decoder. The scanning rate thus becomes
4 times greater (4 x 44.1 kHz = 176.4 kHz). The spectral
lines above 20 kHz up to 176.4 kHz - 20 kHz are filtered
out by the transversal filter. The sample values are
truncated to 14
bits.
The noise shaper subsequently
delays the truncation error by the scan duration and
negatively added to the next sample value. The
guantisizing noise caused by truncation is thereby
largely shifted toward the frequency range above 20 kHz.
The digital signal is converted in IC101 or IC201
(TDA 1540) to an analog signal. In order to filter out
the residual frequency component at n (176.4 kHz
+; 20 kHz), a low pass of the third order (Bessel filter)
has been added to the converter output.
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