Samsung HT-DM150 - ZIVA-5 Controller Pin List (Final); ZIVA-5 Controller Pin List Final Details; SDRAM Controller Block Diagram

Samsung Electronics 8-9
Note: The ZiVA-5 core operates at 1.8V ± 10%. Most I/O interface pins can be interfaced with 3.3-V or 5-V devices depending on the voltage applied to the VDD pins associated
with them. Refer to the Application Note for more information.
190 HCS
4/GPIO[41] 3.3V* I
191 HCS
3/GPIO[42] 3.3V* I
192 HCS
2/GPIO[43] 3.3V* I
193 HCS
1 3.3V* I/O
194 HCS
0 3.3V* I/O
195 GNDP GROUND
ó
196 VDDP 3.3V ó
197 TRST 3.3V* I
198 TDO 3.3V* O
199 TDI/GPI[0] 3.3V* I
200 TMS/GPI[1] 3.3V* I
201 TCK 3.3V* I
202 RESET
3.3V* I
203 ALE
3.3V* I/O
204 GND GROUND
ó
205 VDD 1.8V ó
206 HA3 3.3V* I
207 HA2 3.3V* I
208 GNDP GROUND
ó
Table 1 ZiVA-5 controller Pin List (Continued)
Pin No. Pin Name I/O Voltage I/O Type
13.5 MHz Crystal
Bus Interface Unit
IR IDC
SPARC
Microprocessor
Phase
Lock
Loop
ATAPI
SDRAM Controller
System Control Bus
Audio
Output
Unit
GPIO
SPI
UART1& 2
ZiVA
A/V Core
Audio
Input Unit
Decryption
Track Buffer
Processor
Interlaced/
Prog
Prog
ressive
Video
Encoder
Five 10-bit
Video
DACs
Graphics
Engine
CCIR 656
ASYNC BUS
32-128Mbit