Samsung HT-DM150 - W986432 DH SDRAM Block Diagram

8-10 Samsung Electronics
BLOCK DIAGRAM
DQ0
DQ0
DQ31
DQ31
DQM0~3
DQM0~3
CLK
CLK
CKE
CKE
A10
A10
CLOCK
CLOCK
BUFFER
BUFFER
COMMAND
COMMAND
DECODER
DECODER
ADDRESS
ADDRESS
BUFFER
BUFFER
REFRESH
REFRESH
COUNTER
COUNTER
COLUMN
COLUMN
COUNTER
COUNTER
CONTROL
CONTROL
SIGNAL
SIGNAL
GENERATOR
GENERATOR
MODE
MODE
REGISTER
REGISTER
COLUMN DECODER
COLUMN DECODER
SENSE AMPLIFIER
SENSE AMPLIFIER
CELL ARRAY
CELL ARRAY
BANK #2
BANK #2
COLUMN DECODER
COLUMN DECODER
SENSE AMPLIFIER
SENSE AMPLIFIER
CELL ARRAY
CELL ARRAY
BANK #0
BANK #0
COLUMN DECODER
COLUMN DECODER
SENSE AMPLIFIER
SENSE AMPLIFIER
CELL ARRAY
CELL ARRAY
BANK #3
BANK #3
DATA CONTROL
DATA CONTROL
CIRCUIT
CIRCUIT
DQ
DQ
BUFFER
BUFFER
COLUMN DECODER
COLUMN DECODER
SENSE AMPLIFIER
SENSE AMPLIFIER
CELL ARRAY
CELL ARRAY
BANK #1
BANK #1
NOTE:
The cell array configuration is 2048 * 256 * 32
ROW DECODER
ROW DECODER
ROW DECODER
ROW DECODER
ROW DECODER
ROW DECODER
ROW DECODER
ROW DECODER
A0
A0
A9
A9
BS0
BS0
BS1
BS1
CS
CS
RAS
RAS
CAS
CAS
WE
WE
2.W986432DH