Samsung ML-4550 - Page 29

Service Manual
Summary of Product
3-12
Samsung Electronics
3.3.1.1 Asic (ORION 2)
Marvell Feroceon 2850 ARM Compatoble (I-Cache: 32KB, D-Cache-32KB)
64-bit RISC embedded processor core
Dual bus architecture for bus traffic distribution
- AMBA High performance Bus (AHB)
- System Bus with SDRAM
- 64-bit Mbus Crossbar extension Interface with Flash and Device port
SDRAMC
- 32 Bits Dual mode DDR-II, 200MHz
- 4 Banks (Up to 256MB per Bank)
Device Controller
- Boot Flash 1 Bank (Up to 128MB)
- Device/NOR Flash 3 Banks (Up to 128MB per Bank)
No Graphic Execution Unit and Image processor
No Codec (Encoding / Decoding)
Printer Video Controller Interface for LBP engines
- Hyper-C : Printer Video Controller with RET algorithm
(Line Memory & Lookup Table Memory : 512 x 8 , 4096 x 16)
Dual / Single Beam, LVDS Pad (VDO, HSYNC)
PCI Controller
- 32Bits, 66MHz (PCI) / 133MHz (PCI-X)
- PCI Local Bus Specification rev. 2.2 compliant
- PCI Express Specification beta 1.0a compliant
- Host /Agent Mode (Support 3+4 Express Devices in Host Mode)
Engine Controller (LPEC1)
- LSU Interface unit
- Step Motor: 2 Channels
- PWM: 8 Channels
- ADC: 6 Channels
USB 2.0 Interface with Embedded USB 2.0 PHY
Gigabit Ethernet Controller
- IEEE 802.3 compliant with 10/100/1000 Mbps full-duplex GbE port
- Support GMII,MII and RGMII interface with external PHY/SERDES device
Package : 496pins PBGA
Power : 1.2V(Core), 3.3V(IO) power operation
Speed : 600MHz core(ARM9 Compatible) operation, 200MHz bus operation