Sanyo DC-D9 - Page 38

[C BLOCK DIAGRAM & DESCRIPTION
IC104 CXD2518Q ( DIGITAL SIGNAL PROCESSOR )
No.
Name
1/0
Description
1 SCOR
o Turns “H”
when sync SO or S1 is detected.
2 SBSO
o
Serial output of sub-code P - W.
3
EXCK
I
Clock input
for reading SBSO.
4
SQSO
o Serial output of SUBQ & SOBIT.
5
SQCK
I Clock input
for reading SQSO.
6
MUTE
I
“H” at muting, “L” at muting cancel.
7
SENS
o SENS
signal output to CPU.
8
XRST
f
System reset, “L” at resetting.
9
DATA
I
Inputs serial data from CPU.
10 XLAT
I
Latches input from CPU.
Serial data latches at falling edge.
11 CLOK I
Inputs serial data transfer
clock from CPU.
12
V55
-
GND.
13 SEIN
I
Inputs SENS signal from SSP.
14 CNIN
I
Inputs track jump count signal
15
DATO
o Outputs serial data to SSP
16 XLTO
o
Outputs latches to SSP.
Serial data latches at falling edge.
i7
CLKO
o Outputs serial data transfer clock to SSP.
18 TEST2
I
Pin for TEST. Normal used state VOD.
19 SPOB
I
Not used
20 SPOC
I
Not used
21
SPOD I
Not used
22 XLON
o Interface for extension of M. processor(output )
23 FOK
I
Focus OK signal input pin.
Used servo auto sequencer with SENS output.
24
MON
o ON/OFF control signal for spindle motor.
25 MDP
o Servo control
signal for spindle motor.
26
MDS
o Not
used
27 LOCK
o Not used
28
TEST
I
GND.
29 FILO
o
Output of filter for master PLL.(Slave = Digital
PLL)
30
FILI
I Inputs to filter
for master PLL.
31
Pco
o
Outputs of charge pump for master PLL.
32
VOD
-
Power supply for digital.( + 5V)
33
AVssl
- Power supply
for analog.
34
CLTV
I
VCO control voltage input for master
PLL.
35
AVDO1
-
Power supply for analog.( + 5V)
36
,RF
I EFM signal input.
37
BIAS
I
Inputs constant current for asymmetry
correction circuit.
38
ASYI
I
Inputs comparator voltage for asymmetry
correction circuit.
39
ASYO
o EFM fill swing output.(”L” = Vss, “H” = VDD)
40
ASYE
i
“L” : OFF of asymmetry correction.
“H” : ON of asymmetry correction.
Description
Not used
No.
Name 11/0
WDCK I O
41
42
D/A interface for 48-bit slot.
LRCK O
LR clock (f= FS)
LRCKI
I
Inputs LR clock to DAC.(48-bit slot)
PCMD
o D/A interface. Serial data(2’SCOMP,MBS first)
PCMDI
I
Inputs audio data to DAC.(48-bit slot)
BCK
o
D/A inteflace. Bit clock.
BCKI
I
Inputs bit clock to DAC.(48-bit slot)
GTOP
o
Not used
XUGF
o
Not used
XPCK
o Not used
GFS
o Not used
43
44
45
46
47
48
49
50
51
RFCK I O I Not used
52
53
Vss
-
I GND.
C2P0
O I
Not used
i
54
Not used
Not used
Not used
Not used
*
55
56
57
MNT1 ] O
M!?-D-
58
59
FSIT
0 I Not
used
C4M ! O
I Not used
60
,
DOUT
o Not used
I
61
62
Stays “H” for playback disc provided with I
EMPH
o
Eiz--+
emphasis or “L” for that without emphasis.
63
EMPHI
I
WFCK
o Not used
1
64
65
66
67
68
F
70
71
72
73
74
F
76
77
78
T
80
0
Outputs detection for non-sound data.
“H” at detection for non-sound data (L-ch)
o
Outputs detection for non-sound data.
“H” at detection for non-sound data (R-ch)
I
Normal used state: “L”.
Power supply for DAC.
o Outputs PWM for L-ch. (Positive Phase)
o Outputs PwM
for L-ch. (Negative Phase)
Power supply for L-ch PWM driver.
ZEROL
ZEROR
DTS1
voD
LPWM
NLPWM
AVD02
AVOD3
-
Power supply for X’tal.
XTAI
I
Inputs X’tal oscillation circuit (33.8688 MHz).
XTAO
I Outputs X’tal oscillation circuit (33.8688 MHz).
AV553
- GND.
AV552
- GND.
Outputs PWM for R-ch. (Negative Phase)
Outputs PWM for R-ch. (Positive Phase)
Normal used state “
L“.
VRPWM
o
RPWM
o
DTS2 I
I
I
I Normal used state “L”.
DTS3 I
I
I
I
I
-48–
,’