Sanyo DC-F430AV - Page 32

IC BLOCK DIAGRAM
IC104 CXD2508AQ (Digital Signal Processor)
No. PinName Uo
Function
1 SCOR
o Turns[1-l]when Sync SO or S1is detected.
2
I
SBSO
I
O serialOlitput of sub-code P - W.
3
EXCK I l(lo& inDut for readina SBSO.
1 I
I
4
SQso
o serial
Output of SUBQ (80-bti).
BEiEiza
I [H] at muting, [L] at muting cancel.
9
DATA
I
Inputsserialdatafrom CPU.
10 XLAT
, La&es input from CPU. Serial data latchesat falling
11 CLOK
I Inputs Serial data transfer clock from CPU.
12 Vss
- CND. (OV)
13 SEIN
I InOuts SENS Sional from SSP.
14 CNIN
o Inputs trad( jump count signal.
15 DATO
o o@Duts serialdatato SSP.
1
I 1
16
XLTO
(-J O~ls
latchesto S-SP.Serial data latches af falling
~CLKO I I 10utputsserial data transfercfcckto SSP.
1
1 1
I
18 I SPOA
I
I [lnterfa~ for extension of M. rxocessor (input A).
.,.
19 SPOB
I Interfau for extensionof
M. processor (input B).
m SPOC
I interface for
extension of M. processor (input C).
21 XTSL
I c~stal Sei-ion L: 16.9344MHz, H : 33.8566MHz.
I 1 1
221
XLON O [ Interface for extension of M. txocessor (outDuf).
23
FOK
I
,
Focus OK signal input pin. Used servo aut
sequencerwith
SENS output.
1
1 1
24 I MON
I
O 10 N/OFF control Sianal for .sDindle motor.
25 MDP o
26 MDS o
27 LOCK o
B
TEST I
29
FILO o
3)
FILI I
31 Pco o
22
VDD -
33 AVSS1 -
34 CLTV I
% AVDD1 -
38
RF I
37
BIAS I
28 ASYI I
39 ASYO o
40 ASYE I
~No. I PinName t UO
I
Function
I
II
41 WDCK
I
ol~(~)nterfa~
for 46-bt slot. Ward clock (f .
42 LRCK
I
0 lD/A interfacefor 46-bit slot. LR clock (f= FS).
43
I
LRCKI I I InOuts LR clack to DAC. (46-M dot)
I
I
44 I PCMD
I
O D/A interface. Serial data (2’SCOMP, MBS first)
1
1 1
I
45
PCMDI I lnpms audio data to DAC. (46-bt slot)
II
46
BCK
I
O lD/A interface. Bit dock.
47 BCKI I Ilnputs bi
CIOM to DAC. (48-bti Slot)
1
1 I
t
48 GTOP
I
I lGTOp
Sianal outDut.
I
-,
49
XUGF o
XUGF signal autput.
w
XPCK
o
XPCKsignaloutput.
-.
51 GFS
o
GF.Ssignal
output.
9 RFCK
o
RFCK Signal output.
S3
Vss
-
GND. (OV)
1
I
1
I
54
C2P0
I
O lc2po S.ianalotiD@.
I
-.
55
XROF o
XROFsignal output.
56
MNT3
o
MNT3 Signal output.
1
1
1
I
57
I
MNT1
I
O IMNTI sianaloutrxk
I
56
MNTO
o
MNTo Signal output.
s
FSIT
o
2/3 chided output
of pins73 or 74.
ER?!!59
o Stays [H] for playback disc provided with
emphasisor [L]for that without emphasis.
I
63
I
EMPHI
I
E&f,rnphasis ONIOFF of DAC. [H] at ON, ~] at
-~
Servo control signalfor spindle motor.
O WFCK(Write Frame Clock) signal output.
Servo control signal for spindlemotor.
The oufpd of this pin is [H] when the GFS si nal
sampledat 460 Hz is [H]. If turns jL] when the FS ~
sianalturns out (L18 or moretimes in succession.
Pinfor TEST. Normal used stage: GND.
67
DTS1
I
Test pin for DAC.Normalused state: [L]
Output of tifterfor master PLL. (Slave= DigitalPLL)
@
VDD
- Power supplyfor DAC.
Inputsto filterfor master PLL.
63 NLPWM
o
Outputs PWM for L-ch. (Negative Phase)
Outputsof chargepump for masterPLL.
70
LPWN
o
ou@@j Pwftl for L-ch. (Positive Phase)
Power supply for digital. (+5V)
71
AVDD2
- Power supply for PWM driver.
‘Powersupplyfor analog. (OV
72
AVDD3
- Power supplyfor Xlal.
VCO controlvoltage inputfor master PLL.
73
XTAI I
Inputs Xbl oscillation circuit (33.8688 MHz).
Power supply for analog. (+5V)
74
XTAO
o
Outputs X’tafoscillation circuit (33.8668 MHz).
EFM signal input.
Inputs constant cuwenf for asymmetry correction
?5
AVSS3
- Power supply for X?al. (GND)
circuit.
76
AVSS2
- Power supply for PWM driver.(GND)
Inputscomparator voltagefor asymmetry corwcfion
77 NRPWM
o
ou@ufs PWM for R-ch. (Negative Phase)
circuit.
76
RPWM
EFM fill swing output. ([L]= VSS, [H] = VDD)
o
outputs PWM for R-ch. (Positive Phase)
79
M : OFF d asymmetly correction. [H] : ON d
*
DST2 I Test
pin for DAC. Normal used state: [L]
asymmetly corwction.
DST3 I Test pin for DAC. Normal used state: [L]
-31-