Sanyo DC-X5C - Page 36

- 41 -
IC103 LA6541 (Pick-up Actuator & CD Mechanism Motor)
IC BLOCK DIAGRAM & DESCRIPTION
123456 789 10 11 12
131415161718192021222324
Vcc Vref VIN4 VG4 Vo8 Vo7 GND Vo6 Vo5 VG3 VIN3 CD RES
Vcc Mute VIN1 VG1 Vo1 Vo2 GND Vo3 Vo4 VG2 VIN2 Re
g
OUT Re
g
IN
Vcc
11k
11k
11k11k
Level
Sift
BTL
Driver
BTL
Driver
Level
Sift
RESET
Regulator
Level
Sift
BTL
Driver
Level
Sift
BTL
Driver
2
8
6
7
3
5
1
9
Vcc
Vref
Vs
OUT1
OUT2
GND
IN1
IN2
Protective Circuit
(Heat Interception)
REG
IC131,132 TA7291S (Bridge Driver)
Pin Name Function
1V
CC
Apply voltage of 2.7 - 5.5V to V CC ,
and 0V to V
SS .
2V
REF
Reference voltage input pin for A-
D converter.
3AV
SS Connect V SS.
4P4 4 /INT 3 /PWM
5
6
7
P4
3 /INT 2
P4 2 /INT 1
P4 1
/
INT
0
8-bit CMOS I/O port with the
same function as port P0.
C
M
OS
co
mp
at
i
b
l
e
inp
ut
l
e
v
e
l.
8P4
0 /CNTR 1 CMOS 3-state output structure.
9
P2
7 /CNTR 0/
S RDY
I/O direction register allows each
pin to be individually
pr
og
r
a
mm
ed
as
e
i
t
h
e
r inp
ut
o
r
10 P2
6 /S CLK 8-bit CMOS I/O port.
11
12
P2
5 /SCL 2 /T X D
P2
4 /SDA 2 /R X D
CMOS compatible input level.
P2
0 , P2 1 , P2 4 to P2 7 : CMOS 3-
state output structure.
13
14
16
P2
3 /SCL 1
P2 2 /SDA 1
P2 1 /X CIN
P2 2 to P2 5 can be switched
between CMOS compatible input
level or SMBUS input level in the
I
2
C-BUS interface function.
17 P2
0 /X OUT P2 4 , P2 3 : N-channel open-drain
structure in the I
2
C-BUS interface
function.
P2
2 , P2 3 : N-channel open-drain
structure.
15 CNV
SS
This pin controls the operation
mode of the chip.
Normall
y
connected to V SS
18 RESET Reset input pin for active "L".
19 X
IN
Input and output pins for the clock
generating circuit.
When an external clock is used,
connect the clock source to the
X
IN pin and leave the X OUT pin
open.
20 X
OUT
Connect a ceramic resonator or
quartz-crystal oscillator between
the X
IN and X OUT pins to set the
oscillation fre
q
uenc
y
.
21 V
SS
Apply voltage of 2.7 - 5.5V to V CC ,
and 0V to V
SS .
22
23
24
25
P1
7
P1 6
P1 5
P1 4
8-bit CMOS I/O port.
CMOS 3-state output structure.
26
27
28
29
P1
3
P1 2
P1 1
P1 0
I/O direction resister allows each
pin to be individually
programmed as either input or
output.
CMOS compatible.
30
31
32
33
34
35
P0
7
P0 6
P0 5
P0 4
P0 3
P0 2
P1 3 to P1 7 (5 bits) are enabled to
output large current for LED drive
(M38513E4/M4).
P1
0 to P1 7 (8-bits) are enabled to
output large current for LED drive
(
M38514E6/M6
)
36
37
P0 1
P0 0
38
39
40
41
42
P3
4 /AN 4
P3 3 /AN 3
P3 2 /AN 2
P3 1 /AN 1
P3 0 /AN 0
8-bit CMOS I/O port with the
same function as port P0.
CMOS compatible input level.
CMOS 3-state output structure.
IC190 M38504M6-215FP (Single Micro chip 8-bit)
Ciock generating
circuit
Watchdog
timer
R A M
R O N
A-D
converter
(10)
PWM
(8)
P4(5) P3(5) P2(8) P1(8) P0(8)
SI/O(8)
I C
2
Prescaler 12(8)
Prescaler X(8)
Prescaler Y(8)
Timer 1(8)
Timer 2(8)
Timer X(8)
Timer Y(8)
C P U
A
X
Y
S
PC
L
PS
PC
H
INT 0 -
INT
3
Reset
Sub-
clock
input
X
CIN
Sub-
clock
output
X
OUT
CNTR 0
CNTR 1
XCOUT
XCIN
18 15
1
21
2019
2
34
5
6
7
8
9
10
11
12 13
14
16
17
38 39
40
41
42
22 23
24
25
27
29
30
31
32
33 34
35 36
37
2826
X
IN
X OUT V SS V CC
CNV SS
RESET
P4
4
/INT
3
/PWM
P4
3
/INT
2
P4
2
/INT
1
P4
1
/INT
0
P4
0
/CNTR
1
V
REF
AV
SS
P2
7
/CNTR
0
/S
RDY
P2
6
/S
CLK
P2
5
/SCL
2
/T
X
D
P2
4
/SDA
2
/R
X
D
P2
3
/SCL
1
P2
2
/SDA
1
P2
1
/X
CIN
P2
0
/X
COUT
P3
0
/AN
0
P3
1
/AN
1
P3
2
/AN
2
P3
3
/AN
3
P3
4
/AN
4
P0
0
P0
1
P0
2
P0
3
P0
4
P0
5
P0
6
P0
7
P1
0
P1
1
P1
2
P1
3
/(LED
0
)
P1
4
/(LED
1
)
P1
5
/(LED
2
)
P1
6
/(LED
3
)
P1
7
/(LED
4
)