Sharp CD-XP7700

CD-XP700/CD-XP7700
– 52 –
IC4 VHiLC32V4265B1: 4M (262144 words x 16 bits) DRAM (LC32V4265B)
1 VCC Power supply.
2-5 I/O1-I/O4 Data I/O.
6 VCC Power supply.
7-10 I/O5-I/O10 Data I/O.
11*-14* N.C. Not used.
15 WE Write enable.
16 RAS Low address strobe.
17* N.C. Not used.
18-21 A1-A3 Address input.
22 VCC Power supply.
23 VSS Ground
24-28 A4-A8 Address input.
29 OE Output enable.
30 UCAS Column address strobe. (Lower byte control)
31 LCAS Column address strobe. (Upper byte control)
32*-34* N.C. Not used.
35-38 I/O9-I/O12 Data I/O.
39 VSS Ground
40-43 I/O13-I/O16 Data I/O.
44 VSS Ground
Terminal NamePin No.
Function
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
RAS
UCAS
Clock generator No. 1
Clock generator No. 2
LCAS
A0
A8
Mode control
Refresh counter
Low address
buffer
Column
address buffer
Row decoder
262144 memory cells
x 16 bits
512
512x16
512
Sense ampllfler I/O gate
Column decoder
Pre-decoder
Substrate bias generator
Clock generator No. 3
Lower byte Upper byte
Data input buffer
I/O1 to I/O8 I/O9 to I/O16
Data output buffer
I/O1 to I/O8 I/O9 to I/O16
OE
I/O16
I/O1
WE
VSS
VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
23242526272829303132333435363738394041424344
VCC
I/O1 I/O2 I/O3 I/O4
VCC
I/O5 I/O6 I/O7 I/O8
N.C. N.C. N.C. N.C.
WE
RAS
N.C.
A0 A1 A2 A3
VCC
VSS I/O16 I/O15 I/O14 I/O13 VSS I/O12 I/O11 I/O10 I/O9 N.C. N.C. N.C. LCAS UCAS OE A8 A7 A6 A5 A4 VSS
Figure 52 BLOCK DIAGRAM OF IC