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CD-XP700/CD-XP7700
IC5 RH-iX0505AW00: CD Signal Control (IX0505AW)
1-8 P60/ANI0-P67ANI7 Port6. Analog input.
9 AVSS Analog ground.
10,11 P10, P11 Port1
12 P30/INTP0/TI81/CPT90 Port3. Interrupt from peripherals. Timer input. Capture trigger input.
13 P31/INTP1/TO81 Port3. Interrupt from peripherals. Timer output.
14 P32/INTP2/TO90 Port3. Interrupt from peripherals. Timer output.
15 P33/INTP3/TO82/BZO90 Port3. Interrupt from peripherals. Timer output. Buzzer output.
16 P20/SCK20/ASCK20 Port2. Serial clock. Asynchronous serial input.
17 VDD1 Power supply.
18 P21/SO20/TXD20 Port2. Serial output.Transmit data.
19 P22/SI20/RXD20 Port2. Serial input. Receive data.
20*,21 P23, P24 Port2
22 IC0 (VPP) Internally connected. Programming power supply.
23,24 XT2, XT1 Cryatal (Subsystem clock)
25 RESET Reset
26,27 X2, X1 Cryatal (Main system clock)
28 VSS0 Ground
29 VDD0 Power supply.
30 P25/TI80/SS20 Port2. Timer input. Chip select input.
31* P26/TO80 Port2. Timer Output.
32*-34* P00-P02 Port0
35 P03 Port0
36* P04 Port0
37 VSS1 Ground
38* P05 Port0
39*-42* P50-P53 Port5
43 AVDD Analog power supply.
44 AVREF Analog reference voltage.
Terminal NamePin No.
Function
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17 18 19 20 21 22
23
24
25
26
27
28
29
30
31
32
33
3435363738394041424344
P60/ANI0
P61/ANI1
P62/ANI2
P63/ANI3
P64/ANI4
P65/ANI5
P66/ANI6
P67/ANI7
AVSS
P10
P11
P30/INTP0/TI81/CPY90
P31/INTP1/TO81
P32/INTP2/TO90
P33/INTP3/TO82/BZO90
P20/SCK20/ASCK20
VDD1
P21/SO20/TXD20
P22/SI20/RXD20
P23
P24
IC0 (VPP)
AVREF
AVDD
P53
P52
P51
P50
P05
VSS1
P04
P03
P02
P01
P00
P26/TO80
P25/TI80/SS20
VDD0
VSS0
X1
X2
RESET
XT1
XT2
Figure 53 BLOCK DIAGRAM OF IC
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