®
IC5 VHiSAA731
0/-1
(SAA7310GP)
Pin No.
Terminal
Name
Function
1*
EFAB
Error Flag: output from interpolation and mute
circuit
indicating unreliable data.
2 DAAB
Data: this output together
with
its
clock
(CLAB) and
word
select (WSAB) outputs, conforms to the
12S
bus format.
3 CLAB
Clock: 1
2S
output.
4 WSAB
Word
Select: 1
2S
output.
5 D1NT2
Data interpolated input: this pin should normally be set HIGH. When using the CD3A in a non-digital audio
application this pin should be set LOW (with DEEM/DINT1 set HIGH) to prevent data being interpolated.
6*
TESn
Test output 1
7-14
AO-A7 Address: address outputs to external RAM.
15 RAS
Row Address Select: output to external RAM (4416)
which
uses multiplexed address inputs.
16
R/W
Read/Write: output signal to external RAM.
17*
TEST2
Test output 2
--
Mute: input
from
the microprocessor. When mute is LOW the data output DAAB, pin 2, is attenuated to zero in 15
18 MUTE
successive
divide-by-2
steps. On the rising edge of mute the data output is incremented to the first
'good'
value
in 2 steps. This input has an internal pull-up of 50
kn
(tvp.).
19-21 D1-D3 Data: data inputs/outputs to external RAM.
22
CAS
Column Address Select: output signal to external RAM.
23
D4
Data: data
input/output
to external RAM.
Motor Speed Control: open drain output
which
provides a pulse
width
modulated signal
with
a pulse rate of 88
kHz to control the rate of data entry. The duty factor varies from 1.6% to 98.4% in 62 steps. When a motor-start
24 MSC
signal is detected via pin 42 (SWAB/SSM) the duty factor is forced to 98.4% for 0.2 seconds
followed
by a normal
calculated signal. After a motor-stop signal is detected the duty factor is forced to 1.6% for 0.2 seconds,
followed
by a continuous 50% duty factor.
25 XTAL2
Crystal oscillator output: drive output to
clock
crystal (11.2896 MHz tvp.).
26
XTAL1
Crystal oscillator input: input from crystal oscillator or slave clock.
27 VSS Ground:
circuit
earth potential.
28 VDD
Power Supply: positive supply voltage
(+5V).
29 PD/OC
PhaseDetector output/Oscillator Control input: outputs of the frequency detector and phase detector are summed
internally, then filtered at this pin to provide the frequency control signal for the VCO.
30 Iref
Current reference: external reference input to the phase detector and data slicer. This input is required to minimize
the spread in the charge pump output of the phase detector and data slicer.
Feedback: output from the
input data slicer. This output is a current source of 100
fl
A (tvp.)
which
changes
31 FB
polarity when the level detector input HFI at pin 32 rises above the threshold voltage of 2V (tvp.). When a data
run length violation is detected
(e.q, during drop-out), or when HFD at pin 34 is LOW, this output goes to a high
impedance state.
High-Frequency Input: level detector input to the data slicer. A differential signal of between 0.5 and
2.5V
(peak-
32 HFI
to-peak value) is required to drive the data slicer correctly. When a Tmax violation is detected or when HFD is
LOW, this input is biassed
directly
to its threshold voltage
33*
TEST3
Test output 3
High-Frequency Detector: when HIGH this input signal enables the frequency and phase detector inputs, also the
34*
HFD
feedback output (FB)
from
the data slicer. An internal voltage clamp of 3V (tvp.) requires the HFD input to be fed
via a high impedance. This input has an internal pull-up of
50kn
(tvp.).
35
AM
Additional Mute: This pin is normally held HIGH. Should
track
loss occur the pin should be taken LOW and then
the data is forced LOW at the pre-FIFO stage. The muted data
will
then be corrected after de-interleaving.
--
Counter Reset Inhibit: when LOW this input signal allows the
divide-by-588
master counter in the DEMOD
timing
36 CRI
to run-free. This input has an internal pull-up of
50kn
(tvp.).
37 QDATA
Q-channel Data: this subcoding output is parity checked and changes in response to the Q-channel
clock
input
(see subcoding microprocessor handshaking protocol).
3B
QRA
Q-channel Request
input/Acknowledge
output: the output has an internal pull-up of nominally 'l
Okfr.
(see
subcoding microprocessor handshaking protocol).
39*
TEST4
Test output 4
40 QCL
Q-channel Clock:
clock
input generated by the microprocessor when it detects a QRA LOW signal.
De-emphasis output and data interpolated input: signal derived
from
one bit of the parity-checked Q-channel and
--
fed out via the debounce
circuit
in DEEM mode. When using the CD3A in a non-digital audio application this pin
41
DEEM/DINT1
should be set HIGH (with DINT2 set LOW) to prevent data being interpolated. Note: This pin should only be used
in its input mode when D1NT2 is LOW.
Subcoding
Word
clock
output and Start/Stop Motor input: open drain output
which
is sensed during each HIGH
42 SWAB/SSM
period and if externally forced LOW a motor-stop condition
will
be decoded and fed to the motor control logic
circuit. When allowed to return HIGH, the motor
will
start. This open-drain output has an internal pull-up of
10kn
(tvp.).
43*
SDAB
Subcoding Data: a 10- bit burst of data, including flags and sync bits, is output serially once per frame clocked by
burst
clock
output SCAB.
44*
SCAB
Subcoding Clock: a 1O-bit burst
clock
2.8224 MHz (typ.) output
which
is used to synchronize the subcoding data.
In this unit, the terminal
with
asterisked mark
(*)
is (open) terminal
which
is not connected to the outside.
-60-
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