Sharp HT-SB200 - Page 43

HT-SB200
7 – 8
IC901 VHISTA333BW-1 : 2.1 Channels High Efficiency Digital Audio System ( STA333BW ) ( 1/2 )
Figure 7-6 BLOCK DIAGRAM OF IC
Figure 7-7 PIN CONFIGURATION OF IC
SA
SCL
SDI
LRCKI
BICKI
RESET
INT LINE
PWDN
XTI
PLL_FILTER
Processor
POWER
SDA
I2C
PLL
EQ, Tone,
Volumes...
Serial Data Input
Channel mapping
CONTROL
OUT1A
OUT1B
OUT2A
OUT2B
DDX3A
DDX3B
DDX4A/TWARNEXT
DDX4B/EAPD
CONFIG
STATUS
GND_SUB
V
dd_DIG
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
SA
TEST MODE
GND_DIG
SCL
SDA
INT_LINE
RESET
SDI
LRCKI
BICKI
XTI
PLL_GND
PLL_FILTER
PLL_Vdd
POWRDN
GND_DIG
VDD_DIG
TWARN/OUT4B
EAPD/OUT4B
VSS
VCC_REG
OUT2B
OUT2A
OUT1B
GND2
GND1
OUT1A
GND_REG
CONFIG
OUT3B/DDX3B
OUT3A/DDX3A
Vdd
V
cc2
V
cc1