Sharp IQ-9200

OZ-9600 IT
TQ-9200
@® RESET reset pin
This line is used to initialize the IC. A high on this line initializes all
register contents. In addition to this function, it also has an internal
power-on-reset circuit. The reset is OR’ed with the power-on-reset
circuit. Internal pulldown is not provided on the reset line.
NOTE: The power-on-reset circuit may not start active depending
on how the power is turned on.
@® TEST test pin
Only Seiko Epson may provide it for test of the IC. Normally, it is
internally pulled down. It is suggested to connect with VSS exter-
nally.
6) User circuit
The user circuit consists of 14 input/output lines. ONKEY, RSKEY,
and BTCOV lines are Schmitt trigger inputs that normally pulled down
internally.
The one-shot circuit issues a high level signal (normally low) to the
8/512~9/512 one-shot circuit at a high to low transition of the BTCOV
line. The one-shot circuit has a trigger. The one-shot circuit output-2
has a delay of 1/2024~3.1024 second and continues to sent high
level until the BTCOV line becomes high (normally low).
The VDA signal is an output from the voltage detector A. A high level
signal is issued when normal (voltage found). This signal is at a high
at a time of initialization. The NADOCW signal is an active low ad-
dress 0CH write signal. The DFR signal is a register of a user bit that
sends the input level of D to Q at a low to high transition of signal.
When a low level signal is received by R, the DFR is reset with a low
level signal sent to Q. (XQ is an invert output of Q).
0G
NADOCH
INSRES
7 ake 2212
VDA eee {> 7
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1CEA 21 Ay 7 3iN2
Se >
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Ice 1 22% —~o2 2) TR o22, St?
1.—3 we
ONKEY oe Ij) 1S
e 13 3
RSKEY 241 2] ) ; Be: tho! ee
‘ ae 2 i) 4
BTCOV 2 fo 22 ie
onesHor |
2-4. System gate array (LZ95G33)
1) Brief functional description
@ Memory decode ‘
Used to decode the system ROM, RAM, and IC card memories
that produces a chip select signal for each assigned device.
@ Write pad interface
Has an interface circuitry with the handwrite pad.
@ Optical communication interface
Not only switches the CPU serial port to a normal 15-pin port from
the optical communication, it also modules the optical communica-
tion. ;
@ CDROM interface
Not only switches the normal serial port from the CDROM, it also
switches the CDROM drive, and it controls the communication
with the CDROM drive.
© Tablet conirol
Used to control the tablet input and the’ A/D converter.
© Memory protect
The memory is protected using an external voltage detect IC.
OCE1
SRES
VDETO
-10-
@ EEPROM control
Used. to control the EEPROM access, and has a-function to
replace a part of ROM to a part of the EEPROM.
Used to generate clocks and low battery signal cut out function.