Sharp IQ-9200

OZ-9600
IQ-9200
3)
Block
diagram
(LH1553F
common
driver)
é
sau
if
Pee
:
upplied
to
the
seg
river.
X2
Xt
XC2
XCi
LCK1,
LCK2
Hasitest
i
cserset
secs
H240
FRM
MEMORY
a
CONTROL
Timing
UNIT
generator
a
oscillator [-—
Osc
Control unit
Supplied Contrast ;
from
adjust
latch
PROCESSING
.
ee
LVC.
UNIT
r BUFFER
VR1~8 vcc RW DIS BUSY: AD DIO
;
GND
|
CE
CE2
Supplied tothe CEB
segment driver
Fig.5 LH1553F block diagram
4) Common driver (LH1553F) pin description
V2
ve Display drive power supply
v1
PGND2 |
xC1 utput
XC2 Input LCD clock
GND3__ [GND
TEST? ley
TESTI Stpin
Display off control output
FRM
LRW Segment data read/write signal (segment to segment)
LCK1 :
LOKe Display clock
CPU to data bus input/output
CPU to address bus input
CE1 CPU chip enable signal
CE2 CE1 and CE2: Active high
CEB CEB, Active low
BUSY Busy signal output
CPU read/write signal
cr
m
fe)
Segment local chip enable output (for segment)
Contrast preset (with LVC)
These 8 bits data determine the LVC LCD drive voltage.
STB A high on STB shorts between LCD drive voltage VEE and
GND using 3K resistor.
Logic power supply
x1 Output ;
X41 Input Lock clock :
X2
ane Segment to segment local data bus: Output
: Segment to segment local address
AY3 LCD screen display address (absolute), direction Y
AX3
AX2 Segment to segment local address
LCD screen display address (absolute), direction X