EasyManua.ls Logo

Sharp LC-37XD1RU - Page 15

Sharp LC-37XD1RU
64 pages
Print Icon
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
LC-37XD1E/RU SUPPLEMENT
3 – 3
125 Q13 O 24-bit Output Pixel Data Bus. HDMI-G[5]
124 Q14 O 24-bit Output Pixel Data Bus. HDMI-G[6]
123 Q15 O 24-bit Output Pixel Data Bus. HDMI-G[7]
119 Q16 O 24-bit Output Pixel Data Bus. HDMI-R[0]
118 Q17 O 24-bit Output Pixel Data Bus. HDMI-R[1]
117 Q18 O 24-bit Output Pixel Data Bus. HDMI-R[2]
116 Q19 O 24-bit Output Pixel Data Bus. HDMI-R[3]
113 Q20 O 24-bit Output Pixel Data Bus. HDMI-R[4]
112 Q21 O 24-bit Output Pixel Data Bus. HDMI-R[5]
111 Q22 O 24-bit Output Pixel Data Bus. HDMI-R[6]
110 Q23 O 24-bit Output Pixel Data Bus. HDMI-R[7]
1 DE O Data enable.
2 HSYNC O Horizontal Sync Output control signal.
3 VSYNC O Vertical Syanc Output control signal.
121 ODCK O Output Data Clock. HDMI-CLK
97 XTALIN I Crystal Clock Input.
96 XTALOUT O Crystal Clock Output.
88 MCLKOUT O Audio Master Clock Output.
87 MCLKIN I Audio Master Clock Input Reference.
86 SCK O I2S Serial Clock Output.
85 WS O I2S Word Select Output.
84 SDO O I2S Serial Data Output.
78 SPDIF O S/PDIF Audio Output
77 MUTEOUT O Mute Audio Output.
104 INT O Interrupt Output.
102 RESET# I Reset Pin. Active LOW. 5V Tolerant.
32 DSCL0 I DDC I2C Clock for Port 0. 5V Tolerant.
31 DSDA0 I/O DDC I2C Data for Port 0. 5V Tolerant.
30 DSCL1 I DDC I2C Clock for Port 1. 5V Tolerant.
29 DSDA1 I/O DDC I2C Data for Port 1. 5V Tolerant.
28 CSCL I Configuration I2C Clock. 5V Tolerant.
27 CSDA I/O Configuration I2C Data. 5V Tolerant.
103 SCDT O Indicates active video at HDMI input port.
107 CLK48B I/O Data Bus Latch Enable. 2
34 R0PWR5V I Port 0 Transmitter Detect. 5V Tolerant.
33 R1PWR5V I Port 1 Transmitter Detect. 5V Tolerant.
101 TEST I Test Terminal.
6.7.13.19 VCC - VCC(3.3V)
8.12.18 GND - Ground
10 RSET O Reset Pin.
11 COMP I Comparator
14,17,20,56,81,82,
83,93,100
NC - No internal connection.
9 EVNODD O Even/Odd field for interlaced modes.
40 R0XC+ I TMDS input clock pair. HDMI Port 0.
39 R0XC- I TMDS input clock pair. HDMI Port 0.
44 R0X0+ I TMDS input data pair. HDMI Port 0.
43 R0X0- I TMDS input data pair. HDMI Port 0.
48 R0X1+ I TMDS input data pair. HDMI Port 0.
47 R0X1- I TMDS input data pair. HDMI Port 0.
52 R0X2+ I TMDS input data pair. HDMI Port 0.
51 R0X2- I TMDS input data pair. HDMI Port 0.
59 R1XC+ I TMDS input clock pair. HDMI Port 1.
58 R1XC- I TMDS input clock pair. HDMI Port 1.
63 R1X0+ I TMDS input data pair. HDMI Port 1.
62 R1X0- I TMDS input data pair. HDMI Port 1.
67 R1X1+ I TMDS input data pair. HDMI Port 1.
66 R1X1- I TMDS input data pair. HDMI Port 1.
71 R1X2+ I TMDS input data pair. HDMI Port 1.
70 R1X2- I TMDS input data pair. HDMI Port 1.
22,23,35,74,79,92,
105,114,128,139
CVCC18 - Digital Logic VCC. (1.8V)
21,24,36,73,80,91,
106,115,127,138
CGND - Digital Logic GND.
5,16,26,76,89,109,
122,134
IOVCC - Input/Output Pin VCC. (3.3V)

Related product manuals