Sharp SM-SX100 - Schematic Diagram (5;9)

SM-SX100
– 31 –
7
8 9 10 11 12
Figure 31 SCHEMATIC DIAGRAM (5/9)
12
11
10
9
8
7
6
5
4
3
2
1
DGND_AD
DGND_AD
DGND_AD
DGND_AD
+B
+B
+B
+B
14
13
12
11
10
9
8
7
6
5
4
3
2
1
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DGND_SW
DGND_SW
GND
GND
VCC
VCC
+B
+B
+B
+B
+B
+B
+B
+B
+B
+B
+B
DGND_SW
–B
+B
+B
+B
+B
+B
+B
9
8
7
6
5
4
3
2
1
NC
NC
RESET
+5V
(RELAY)
AGND
DGND
+5VD
+5VA
–22V
AGND_AD
DGND_AD
9
8
7
6
5
4
3
2
1
9
8
7
6
5
4
3
2
1
CNP109
TO MAIN PWB
P29 9 - A
+B
+B
+B
–B
–B
G
12
11
10
9
8
7
6
5
4
3
2
1
NC
NC
–
+
+B
DGND_SW
AGND_SW
–
B
–B
AGND_SW
+B
+B
–B
–B
NC
NC
R+
R–
3
2
1
3
2
1
3
2
1
+32V
AGND
–32V
CNP102
TO MAIN PWB
P29 11 - A
P29 10 - A
TO RELAY PWB
NC
NC
L+
L–
TO RELAY PWB
P29 10 - A
–B
AGND_SW
AGND_SW
BLA18 BLA21
BLA23 BLA20
BLA25 BLA24
BLA19 BLA22
CA50
100/50
CA51
100/50
VRA1
200(B)
RA101
6.8K
RA61
680
CA52
100/50
COREA14
COREA12
COREA10
COREA13
COREA11
COREA9
COREA7
CNWAM4ACNWAM4B
CNPA8
CNPA6
COREA4
COREA5
CNWAM3ACNWAM3B
BLA6
CA13
100/16
BLA5
BLA3
BLA4
CA14
100/16
BLA1
BLA2
CA21
0.22
CA22
0.22
ICA3
TAC08F
AND GATE
ICA2
74AC00F
NAND GATE
CA9
18P(CH)
CA8
18P(CH)
CXA1
11.2896MHz
CA11
0.22
CA10
0.22
CA12
0.22
S
ION
RA803
16/5W
RA801
16/5W
CA809
0.22
CA807
0.22
CA805
0.22
LA807
75µH
LA803
10.8µH
LA805
5.6µH
5.6µH
75µH
CA803
0.56
LA801
10.8µH
CA801
0.56
CA806
0.22
CA808
0.22
RA802
16/5W
RA804
16/5W
LA808
75µH
CA810
0.22
LA806
5.6µH
5.6µH
75µH
CA802
0.56
CA804
0.56
LA802
10.8µH
LA804
10.8µH
RLYA1
RA66
2.4K
RA104
6.8K
RA65
2.4K
RA103
6.8K
DA17
DA119
RA63
750
RA64
750
VRA2
200(B)
R
A102
6.8K
RA62
680
RA68
1.3K
RA67
1.3K
1BIT AMP.PWB–B
N
T
-
BIT AMP
EDBACK
LEVEL
J
USTMENT
4.96V(0V)
4.8V
5V
5V(8Ω)
0V(4Ω)
Note) GND makes the point of AGND reference at the time of the instrumentation.
–31.8V(8Ω)
–24V(4Ω)
31.8V(8Ω)
24V(4Ω)
–22.2V(8Ω)
–14.4V(4Ω)
5V(8Ω)
0V(4Ω)
5V
2.5V
2.5V
2.5V
2.5V
5V
5V
1.3V
2.2V
0V
0V
ed.).
8
• The numbers 1 to 8 are waveform numbers shown in page 50.