Siemens 7SR210 - Figure 5.1-2 - Single Stage Circuit Breaker Fail Timing; Figure 5.1-3 - Two Stage Circuit Breaker Fail Timing

7SR210 & 7SR220 Applications Guide
50BF DTL1/50BF DTL2
The time delays run concurrently within the relay. The time delay applied to the CB Fail protection must be in
excess of the longest CB operate time + relay reset time + a safety margin.
First Stage (Retrip)
Trip Relay operate time 10ms
Reset Time 20ms
CB Tripping time 50ms
Safety Margin 40ms
Overall First Stage CBF Time Delay 120ms
Second Stage (Back Trip)
First CBF Time Delay 120ms
Trip Relay operate time 10ms
CB Tripping time 50ms
Reset Time of measuring element 20ms
Margin 60ms
Overall Second Stage CBF Time Delay 260ms
The safety margin is extended by 1 cycle for the second CBF stage as this will usually involve a back-trip of a
Busbar tripping scheme.
The timing sequence for each stage of the circuit breaker fail function is as below.
CB Backtrip
Sucessful
20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340
System
Fault
ms from fault
occuring
Relay
Operation
and CBF
Timer
Started
Main
Trip
Relay
Operation
Failure of
CB to trip
Reset of
CBF elements
does not occur
Backtrip
Operation
Backtrip
Trip Relay
CB Operate Time
Stage 1 CBF Timer (Backtrip) = 120ms
Figure 5.1-2 - Single Stage Circuit Breaker Fail Timing
Stage 1 CBF Timer (Retrip) = 120ms
Failed CB Retrip
Operation
40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 360340
System
Fault
Relay
Operation
and CBF
Timer
Started
Main
Trip
Relay
Operation
CB's
Fails to
Trip
No Reset of
CBF elements
CBF Retrip
Operation
CBF Retrip
Trip Relay
CB Operate Time
Stage 2 CBF Timer (Backtrip) = 250ms
No Reset of
CBF elements
CBF Back trip
Operation
Backtrip
Trip Relay
Operation
Operation of all
BB CB's
Reset of
CBF elements
ms fro
m
occur
i
Figure 5.1-3 - Two Stage Circuit Breaker Fail Timing
©2011 Siemens Protection Devices Limited Page 35 of 40