Release 1.0
Technical Documentation 01/2006
TD_Repair_L3_SXG75_R1.0.pdf Page 65 of 73
13. Bluetooth
SXG75 contains a BCM2004 Bluetooth RF module. The BCM2004 is powered from VREG_MSMP
(2.6V) for the digital interface, and VREG_AUX2 (2.85V) for the RF/core stages. The IC contains an
internal regulator which regulates VREG_AUX2 down to VDD_BT (1.8V).
The Bluetooth baseband processor is contained within the MSM6250. The dedicated Bluetooth
interface between the two devices consists of a synchronous serial bus to transfer configuration and
control messages, a synchronous serial bus to transfer channel data and logic control signals.
Interface signal functions are described below:
Signal Function
Logic input from MSM6250 GPIO.
BT_ENABLE This signal was previously used to enable the VDD_BT regulator. On the
final version of Wolf 5 the control is no longer used, and the regulator is
permanently enabled by pull-up resistor R1607.
BT_CLK
Logic output to MSM6250 Bluetooth interface. System clock, 12 MHz
clock output derived from the BUFF_TCXO_BT reference.
BT_DATA
Logic I/O to MSM6250 Bluetooth interface. Bi-directional Tx and Rx
Channel data interface signal.
BT_TX_RX_N
Logic input from MSM6250 Bluetooth interface. Multi-Purpose Pin: Rx Slot
- Rx_Enable and synchronization detection; Tx Slot - Tx_En and Tx path
data transfer indication.
BT_SDST
Logic input from MSM6250 Bluetooth interface. Serial interface mode
control.
BT_SBDT
Logic IO to MSM6250 Bluetooth interface. Serial interface data.
BT_SBCK
Logic input from MSM6250 Bluetooth interface. Serial interface clock.
19.2MHz master clock input.
BUFF_TCXO_BT The TCXO clock is buffered by the single-gate inverter, D1300. The in-
verter is configured to operate as a linear buffer by C1332/R1310. The
buffer is only enabled when the input VREG_AUX2 is high. This prevents
the clock from being applied when Bluetooth is disabled.
Bluetooth module interface signals
Company Confidential
2006©BenQ
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