Release 1.0
Technical Documentation 01/2006
TD_Repair_L3_SXG75_R1.0.pdf Page 23 of 73
6.3 MSM6250 interfaces
6.3.1 Logic interfaces
Each IO pin on the MSM6250 has an associated pad group. The pad group, and hence the IO pin, is
powered from the supplies as below:
Pad
Group
Supply Name Value Pad Group Connections
1 VREG_MSME 1.850 V (±3%) EBI1 bus to SDRAM
2 VREG_MSME 1.850 V (±3%) EBI2 bus to NAND FLASH and LCD. Plus some GPIO
3 VREG_MSMP 2.600 V (±3%) Most peripheral interfaces
4 VREG_MSMP 2.600 V (±3%) SIM bus (to PM6650). Plus one GPIO.
MSM6250 pad group supplies
The maximum and minimum possible logic levels seen on the I/O pins (allowing for maximum supply
variation and loading) should be within:
Pad
Group
VOL
min
(V)
VOL
max
(V)
VOH
min
(V)
VOH
max
(V)
ViL
min
(V)
ViL
max
(V)
ViH
min
(V)
ViH
max
(V)
1, 2 0 0.45 1.344 1.906 -0.3 0.628 1.239 2.085
2, 3 0 0.45 2.027 2.678 -0.3 0.883 1.741 2.822
MSM6250 logic specification
Peripheral systems on the phone are controlled by the MSM6250 logic signals listed below. These
signals uses General Purpose IO (GPIO) pins on the MSM6250 and are configured to perform the
required function by software.
A brief description of the signals is given in the following table:
Company Confidential
2006©BenQ
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