EasyManua.ls Logo

Sinee EM100-0R4-1B - F08 Group: Preset Speed and PLC Parameters

Sinee EM100-0R4-1B
120 pages
Print Icon
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
User Manual
EM100 Mini Inv
e
For instance: SO
U
the first correspo
n
i.e. F07.15=1110
No. Fun
c
F07.17
Disa
b
Trips
Bit setting value
After detecting t
h
status.
Bit setting value
After detecting t
h
protection.
F07.17 is bit ope
r
following table,
f
protection, i.e.F0
7
corresponding to
1. Never
d
inverter d
2. Refer to binary
3. OLP detection
i
F08 Group: Pre
s
No. Functi
o
F08.00
Preset
S
F08.01
Preset
S
F08.02
Preset
S
F08.03
Preset
S
F08.04
Preset
S
F08.05
Preset
S
F08.06
Preset
S
F08.07
Progra
m
e
rter
9
1
U
and OL fault retry are per
m
n
ding bit of SOU=0 and the
4
1101
c
tion Range
b
led
58 Bits
* EED E
H
0 0 0
14 Bits
tbr OLP IL
P
0 0 0
0: Enabled
1: Disabled
SLU is LSB, arrang
e
order, the 8
th
b
it is n
o
=0
h
e fault corresponding to the
b
=1
h
e fault corresponding to the
b
r
ation, only set correspondin
g
f
or instance: Only set the 2
nd
b
7
.17=00000010. Set the 3
rd
bi
EHt=1 to disable OLP and E
H
d
isable any trip
p
rotection fu
n
amage if there is no protectio
n
system parameter setting des
c
i
s enabled when the absolute
v
s
et Speed and PLC Parame
t
o
n Range
S
peed 1
0.00 Fm
a
S
peed 2
0.00 Fm
a
S
peed 3
0.00 Fm
a
S
peed 4
0.00 Fm
a
S
peed 5
0.00 Fm
a
S
peed 6
0.00 Fm
a
S
peed 7
0.00 Fm
a
m
Operation
Ones place:
O
1
m
itted, other fault retries are p
r
4
th
corresponding bit of OL=0
,
Unit
D
H
t OL
0
P
SLU
0
e
in logical
o
t use
d
b
it, inverter stops output and t
b
it, inverter remains previous
g
bit to protection= 0/1.As sh
o
b
it corresponding to ILP=1 to
i
t corresponding to OLP=1 a
n
H
t, i.e. F07.17=01000100.
n
ction unless special require
m
n
trip after fault occurs.
c
ription of F02.06.
v
alue of output frequency>5.
0
t
ers
Unit
a
x
Hz
a
x
Hz
a
x
Hz
a
x
Hz
a
x
Hz
a
x
Hz
a
x
Hz
O
ptions of program
r
ohibited. Set
,
other bits=1,
D
efault Type
0000
0000
hen enters fault
status without
o
wn in the
disable ILP
n
d the 7
th
bit
m
ent, in case of
0
0Hz.
D
efault Typ
e
0.00
5.00
10.00
15.00
20.00
25.00
30.00
00

Table of Contents

Related product manuals