Sony CDP-411 - Page 16

Zz
1)
45
46
47
DATA |_| DA 14 output when PSSL=1. 64-bit slot data when PSSL=O
bh
[oe]
49
LRCK | 0 | DA T2 output when PSSL=1, 64-bit slot data when PSSL=O
ro :
Q oO
51
52
53
55
56
57
58
59
C2PO [oA Of output when PSSL.=1. COPO output when PSSL=O |
MINTS
MNT?
MNT1 DA 02 output when PSSL=1. MNT1 output when PSSL =0
MNTO DA 01 output when PSSL=1. MNTO output when PSSL=0
XTAI
XTAO
XTSL
61
62
63
X’tal oscillator circuit input
[o>] ol
oO
=
FSTI
FSTO
C
C16M
MD2
DOUT
EMPH
67
aN =
wo)
B
[Digtal-out ON/OFF control pin ———SSSCSCS~SYS
Fo | pieitai-out output pin ——SSSSSSCSC~—~—CS~CS~S~S~S
To [ avback ise output in emphasis mode ——SSCSCS~S~S~S~S~S
week ‘| 0 | WRCK ouput —SSCSC“~“*S*~*~‘“~*~*~*~*Y
£050 o[/Ssub-P through Sub-W seral outpat——SSSSCSC~S~S~S~S
To | su.
Toa
Sub-Q 80-bit output
Clock input for SQSO read-out
71
72
73
74
75
76
77
78
79
SUBQ
SQCK
81
82
83
84
85
DIRC
SCLK
eal on
Ca [teed in I-tack ump mode SSCS
DFSW
87
88