SECTION 2
1C
FUNCTION DESCRIPTION
IC101
(CXA1372Q) PIN
DESIGNATION
Pin No.
1
Pin
Name I/O
Pin
Description
II
VC GND
when two
(±)
dual power supplies
are in use, or
the center voltage (2.5 V)
when a single
power supply is in use.
2 FGD
I Time constants for
gain switching in normal
mode/down mode and
for focus
gain
are
3
FS3
I connected
between the FGD and FS3 pins.
4 FLB
I The capacitor for low
frequency boost In the
focus servo loop
is connected.
5 FEO 0
Focus drive output
6
FE-
I Inverted input to focus
amplifier
7
SRCH I
Time constants to generate the focus
search
waveform are connected.
8
TGU I Time constants
for gain switching in normal mode/up
mode
and for tracking gain are
9
TG2 I
connected between TGU pin
and
TG2
pin.
10
AVCC Analog power
supply
(5 V
when
± dual power supplies are in use, 5
V when a single
power supply is in use.)
11 TAO
0
Tracking drive output
12
TA- I
Inverted input to tracking
amplifier
13 SL
+ I Non- inverted input to
sled amplifier
14 SLO 0
Sled drive output
15 SL-
I
Non- inverted input
to
sled amplifier
16 ESET
I The 610- kQ
phase compensator resistor is
connected to this pin.
17 ISET
I The current
setting resistor is connected to
this pin.
18
SSTOP I
The limit switch is connected to
this pin.
19 AVEE
Analog power
supply (-5V when
±
dual
power supplies are in use, or
GND when a single
power supply is in use.)
20 0mc
I Direct
control pin.
21 LOCK
Sled run- away
prevention circuit operates
when this signal is “L".
22 CLK
Serial data transfer
clock input that is
supplied from CPU (or DSP).
23 XLT
Latch input from CPU
(or DSP).
24
DATA I
Serial data input from CPU
(or
DSP).
25
XRST I System
reset “L"
to
reset.
26
C.OUT 0 Output to
tracking counter.
27 SENS 0
SENS output
28
DGND
Digital ground (GND). (GND
when ± dual power
supplies are in use. GND
when
a
single
power supply is in use.)
29
MIRR 0
Mirror output.
30
DFCT 0
Defect
output.
"H" when defective.
31
ASY I
Auto-assymmetry control input.
32 EFM 0
EFM comparator output
33 FOK
0 Focus OK.
34 CC2 I
Defect-bottom-hold input (input by
capacitive coupling).
35
CCl 0
Defect- bottom- hold output.
36
DVCC Digital
power supply
(+5
V when ± dual power
supplies in
use.
+5
V when a
single
power supply is in use.)
37
CB I The
defect-bottom-hold capacitor is connected to this
pin.
38 CP
I The mirror hold capacitor is connected to
this pin.
39
RFl I
RF signal input (input
by
capacitive
coupling).
40 RFO
I RF signal input (input by DC coupling).
41 DVEE
Digital power
supply
(-5
V when
± dual power supplis are in use. GND
when
a
single
power supply is in
use.)
42 TZC
I Tracking zero cross comparator input.
43 TE I
Tracking
error input
44 TDFCT I The defect prevention hold capacitor is connected to
this pin.
45 ATSC I Anti-shock input.
46 FZC I
Focus zero-cross comparator input.
47 FE I Focus
error input.
48 FDFCT I
The defect prevention
hold
capacitor is connected
to
this pin.
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