Sony fcb-ev7500 - LVDS Receiver Circuit Example (Single Output)

55
Specifications
FCB-EH6500(GB) A-EEP-100-11(1)
LVDS receiver circuit example (Single output)
D3 . 3V _
CN 6 01
30 P
1TX O UT 4 - 2TX O UT 4 + 3TX O UT 5 - 4TX O UT 5 + 5RE S ET 6NC 7TX O UT 6 - 8TX O UT 6 + 9TX O UT 7 -
10TX O UT 7 + 11GN D 12GN D 13UN R EG 14UN R EG 15UN R EG 16UN R EG 17UN R EG 18RX D 19TX D 20GN D 21TX O UT 0 - 22TX O UT 0 + 23TX O UT 1 - 24TX O UT 1 + 25TX O UT 2 - 26TX O UT 2 + 27TX C LK O U T- 28TX C LK O U T+ 29TX O UT 3 - 30TX O UT 3 +
RE S ET
C6 0 1
10 u 25 V
RX D
C6 0 2 0. 1 u
25 V
C6 0 7
0. 1 u
25 V
R6 0 2 1 00
UN R EG
R6 0 4 1 00
TX D
FB 6 02
R6 0 1 1 00 R6 0 3 1 00 R6 0 5 1 00
IC 6 01
TH C 63 L V D1 0 2 4- 1 LT N
1
PG N D_ 1
2
PV C C_ 2
3
RE S ER V E D
4
PD W N
5
MO D E0
6
MO D E1
7
DK
8
R/ F
9
OE
10
MO D E2
11
MA P
12
VC C _1 2
13
GN D _1 3
14
R2 0
15
R2 1
16
R2 2
17
R2 3
18
R2 4
19
R2 5
20
R2 6
21
VC C _2 1
22
GN D _2 2
23
R2 7
24
R2 8
25
R2 9
26
G2 0
27
G2 1
28
VC C _2 8
29
VC C _2 9
30
GN D _3 0
31
G2 2
32
G2 3
33
G2 4
34
G2 5
35
G2 6
36
G2 7
37
G2 8
38
VC C _3 8
39
GN D _3 9
40
G2 9
41
B2 0
42
B2 1
43
B2 2
44
B2 3
45
B2 4
46
VC C _4 6
47
GN D _4 7
48
B2 5
49
B2 6
50
B2 7
51
B2 8
52
B2 9
53
VC C _5 3
54
GN D _5 4
55
CO N T2 1
56
CO N T2 2
57
VC C _5 7
58
GN D _5 8
59
GN D _5 9
60
CL K OU T
61
CV C C
62
CG N D
63
R1 0
64
R1 1
65
R1 2
66
R1 3
67
R1 4
68
R1 5
69
R1 6
70
VC C _7 0
71
GN D _7 1
72
R1 7
73
R1 8
74
R1 9
75
G1 0
76
G1 1
77
G1 2
78
G1 3
79
G1 4
80
VC C _8 0
81
GN D _8 1
82
G1 5
83
G1 6
84
G1 7
85
G1 8
86
G1 9
87
B1 0
88
VC C _8 8
89
GN D _8 9
90
B1 1
91
B1 2
92
B1 3
93
B1 4
94
B1 5
95
B1 6
96
B1 7
97
VC C _9 7
98
GN D _9 8
99
B1 8
10 0
B1 9
10 1
HS Y NC
10 2
VS Y NC
10 3
DE
10 4
CO N T1 1
10 5
CO N T1 2
10 6
VC C _1 0 6
10 7
PV C C_ 1 0 7
10 8
PG N D_ 1 0 8
10 9
LG N D_ 1 0 9
11 0
RA 1 -
11 1
RA 1 +
11 2
RB 1 -
11 3
RB 1 +
11 4
LV C C_ 1 1 4
11 5
LG N D_ 1 1 5
11 6
RC 1 -
11 7
RC 1 +
11 8
RC L K-
11 9
RC L K+
12 0
LV C C_ 1 2 0
12 1
LG N D_ 1 2 1
12 2
RD 1 -
12 3
RD 1 +
12 4
RE 1 -
12 5
RE 1 +
12 6
LV C C_ 1 2 6
12 7
LG N D_ 1 2 7
12 8
RA 2 -
12 9
RA 2 +
13 0
RB 2 -
13 1
RB 2 +
13 2
LV C C_ 1 3 2
13 3
LG N D_ 1 3 3
13 4
RC 2 -
13 5
RC 2 +
13 6
LG N D_ 1 3 6
13 7
LG N D_ 1 3 7
13 8
LV C C_ 1 3 8
13 9
LG N D_ 1 3 9
14 0
RD 2 -
14 1
RD 2 +
14 2
RE 2 -
14 3
RE 2 +
14 4
LG N D_ 1 4 4
14 5
Y3
DE C2
Y1
VS Y NC C1
Y7
CL K
Y4
C5
Y6
C3
Y0
C6 C4
Y5 Y2
HS Y NC C0
C6 0 3 0. 1 u
25 V
C6 0 4 0. 1 u
25 V
C6 0 5 0. 1 u
25 V
C6 0 6 0. 1 u
25 V
C6 1 0
0. 1 u
25 V
C6 1 2
0. 1 u
25 V
C6 1 3
0. 1 u
25 V
C6 2 0 0. 1 u
25 V
C6 1 9 0. 1 u
25 V
C6 1 8 0. 1 u
25 V
C6 1 7 0. 1 u
25 V
C6 1 5 0. 1 u
25 V
C6 1 4
0. 1 u
25 V
C6 1 1
0. 1 u
25 V
C6 0 9
0. 1 u
25 V
C6 0 8
0. 1 u
25 V
FB 6 01
FB 6 03
C6 1 6 0. 1 u
25 V
R6 1 0
10 k
R6 1 2
10 k
R6 1 1
10 k
R6 0 6 1 00 R6 0 7 1 00 R6 0 8 1 00 R6 0 9 1 00
S6 0 1
R6 1 3
10 k
R6 1 4
10 k
GN D
C7
R6 1 5
10 k
10 0
• •
Im p e d a n c e
SW 1, 2 : a d j u s t d e l a y SW 3: s w i t c h L V D 1 0 2 4 R / F
3 0pin C o a x ial
8 lane
• No.1 and 2 of S601 adjust the signal delay. No.3 selects whether to input the rising edge or falling edge of the
signal.