Sony ICF-7600DA - Page 16

1-3.
OUTLINE
OF
TERMINALS
OF
THE
LCD
DOT-MATRIX
SEGMENT
DRIVER
IC202,
MSM5259GS
a
o
a
43)
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@9)
01 (1) 2]
02 @)
03 G)
04 @)
0s 6)
06 6)
07 @)
08 (8)
03 Q)
O10 (0)
on ()
012
013 (3)
014 (4)
@ Pin 51 (DI1)
Receives data from the shift registor of the first
through twentieth bit, and accepts display data
synchronizing with the clock signal in accordance
with the truth values.
Pin 50 (CP)
Receives the clock pulse of the shift registors, and
the data are shifted at the trailing edge of the
clock pulses. A setting-up and holding durations
are required in between the DI1 mentioned
above and this signal CP. The risetime and the
falltime of the clock pulse are to be less than 1
sec.
Pin 44 (DO20)
Transmits the twentieth bit of the shift registor.
Data received at the DI1 mentioned above are
transmitted from this terminal being delayed
with the duration of twenty bits of the shift
registor and, at the same time, synchronized
with the clock pulse.
When this terminal is connected to the D121
terminal, pin 43, a 40-bit shift registor is made.
Pin 43 (DI21)
Receives data of twenty-first through fourty-first
bits of the shift registor. When this terminal is
connected to the DO20 terminal, pin 44, as men-
tioned above, a 40-bit shift registor is made.
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@ Pin 42 (D040)
Transmits the fourtieth bit of the shift registor.
Data received at the DI21 mentioned above are
transmitted from this terminal being delayed
with the duration of twenty bits of the shift
registor and, at the same time, synchronized with
the clock pulse.
When an expansion of handling the numbers of
characters is needed, a cascading connection to
the next stage is required.
Pin 53 (DF)
Receives a signal to accommodate the alternating-
current synchronization for the waveforms of
the LCD-driving signals.
Pin 52 (LOAD)
Input terminal to latch the contents of the shift
registor. In the high (‘‘H’’) conditions, the con-
tents in the shift registor are transfered through
the level shifter to the four level drivers.
In the low (‘“‘L”’) state on the contrary, this ter-
minal retaines the last data of them in the high
(“‘H”’) state, and thus the outputs from terminals
01 through 040 do not change even when the
contents in the shift registors are changed.