Sony ICF-7600DA - Page 17

@ Pin 49 (VDD) and Pin 48 (VSS):
Pin 49 (VDD) is the power-supply voltage input
terminal of this IC, and it receives voltage nomi-
nally in the range of 2.5 VDC to 6.0 VDC.
Pin 48 is the grounding terminal of this IC, it
connects to the ground foil, ie., VSS = 0 VDC.
@ Pin7 (V2), Pin 6 (V3) and Pin 5 (V5)
The bias-voltage supply terminals to drive the
LCD. When static displays are required, V2 and
V5 are to be connected to the VSS terminal, and
at the same time, V3 is to be connected to the
VDD terminal. The common signal is input to
the DF terminal and the buffer gates. The
COMMON signal to drive the LCD is made
through the buffer gates.
TIMING CHARTS
@ Pins 1 through 20 (01 through O20) and Pins 22
through 41 (O20 through 040):
Output driving signals from the internal four-
level drivers. Each output signal directly coin-
cides with each bit.
By combining the contents of the latches and the
DF signal, four levels for the VDD, V2, V3 and
V5 are selected as shown in the table.
LATCH DATA
DRIVE OUTPUT
DF (O1 THROUGH 040)
SELECTED
“oy? V5
(SELECTABLE) VDD
| H |
! L
“D> H V3
(NONSELECTABLE) | L v2
Hl
DATA-TRANSFERRING TIMING CHART:
OUTPUT(IC IN)
TIMING CHART IN STATIC FORM:
of comm J LE LIL
(INPUT)! SIGNAL !
On (OUTPUT)
(WHEN LIT) | | | | | |
On (OUTPUT) | | | | | |
(WHEN UNLIT)
n:1—40
PARTIAL DISPLAYING CIRCUIT (EXAMPLE)
In case of the statical display, LCD-drive bias
supplies V2 and VS are to be connected to VSS, and
further, V3 is connected to VDD terminal. Then,
the common signal is input to the DF terminal, and
also input to the common terminal of the LCD
panel through the buffer gates.
Voo,V3
Vss, V5,V2
Vbpb,V3
Vss ,V5,V2
VOD _MSM5259GS-K
COMMON
SIGNAL
LCD-PANEL
(STATIC)
MSM4069RS
32 ~120Hz
Duty 50%
CONN N SIGNAL
LOAD JL
DATA IN
SHIFT_CLOCK
SUL
MSM 5259GS-K
DI 21
DO20
247