Sony ICF-7600DA - Page 6

SYMBOL
NAMING
DESCRIPTION
1 THRU 10
LCD9
THRU
LCD1
LCD
SEGMENT
SIGNALS
Transmit the segment-output signals to the LCD panel. When matrixes are configured
together with the COM1 thru COM3, a display of 48 dots can be made. These output signals
are output when the LCDD commands are made.-The LCD-driving voltages are of 3.1V typi-
cal, 1/2 bias and 1/3 duty when the frame frequency is 100 Hz.
These LCD11 through LCD16 can also be used at the same time as the key source signals for
the key matrix. These signal are output on time-division bases, and they are output as the
key-source signals at the repetition rate of 6.7 msec.
Whether the key-source signal are to be output while having displays on the panel is depend-
ent upon and selectable by the programs used.
These terminals become automatically in the ““L” (low) state, i.e., non-display mode, at the
power-on reset (VDD changes from low to high state) and at the stoppage moment of the
clock. The display mode does not change at the reset moment in which CE changes from low
to high state. :
11 THRU
13
LCD
COMMON
SIGNAL
VDP
(POWER-
OUTPUT)
CGP
(MUTE/
BUZZER)
CAPACITOR
CONNECTION
TERMINAL
FOR
DOUBLER
VARIABLE
DUTY
PORT
(POWER-
SUPPLY
CONTROL
SIGNAL)
CLOCK
GENERATOR
PORT
(MUTE/
BUZZER
SIGNAL)
INPUT
OF POWER
SUPPLY
VOLTAGE
Transmit common signals to the LCD panel. When the matrixes are configured together with
the LCD1 through LCD16, a display of 48 dots can be made.
Three distinctive signals of VSS3, VSS2 and VDD are output through these terminals at the
repetition rate of 50 Hz.
These terminals become automatically in the ‘““L”’(low) state, i.e., non-display mode, at the
power-on reset (VDD changes from low to high state) and at the stoppage moment of the
clock.
Capacitor-connection terminals to make a
proper voltage doubler to build the 3.1V typi-
cal LCD-driving voltage VDD.
Normal circuit configuration is as follows.
Outputs the variable-duty or the one-bit (PG2) signal. The selection of either of them is
programmable. When used as the VDP, this terminal transmits the pulse chain of 1.12 kHz
continuously, and its duty can be selected from the available 64 steps.
26.7 us 867 us 2 65
= uw ir
893us 893us 67 67
This port can be used as a D/A converter by adding-an integration circuit to this terminal.
Outputs the clock-generator or the one-bit (PD3) signal.
The selection of either of them is programmable. When used as the CGP, this terminal can
transmit the pulse chain of 1 kHz of 46.6% duty or 3 kHz of 60% duty.
In this set, this port outputs a signal to mute noises encoutered in the unlocked condition
of the PLL. When the buzzer output is specified to be output in the alarm operation, this
port outputs the buzzer signal of 1 kHz.
Receives the power-supply voltage for this device. In operation, a voltage of 2.2 to 3.5 VDC
is applied to this terminal. The input voltage can be lowered down to 2.0 VDC when any of
the interna] data in the RAM, i.e., when the CKSTP command is under execution, is to be
holded.
The power-on reset circuit of device starts to operate at the instance this terminal receives
a voltage of 0 (zero) to 2.0 VDC, and the program starts from the location 0 (zero).
Note: This pin and pin 46 are connected internally. So, it is not necessary to apply the
power-supply voltage to both of them. The ceramic-packaged device, however, has
a not-to-be connected pin 46, i.e., N.C. terminal.
CONTROL-
SIGNAL
INPUT
FOR
DIVIDER
Determines the dividing ratio of the fixed-division prescaler.
A 1/4 dividing ratio is made when this terminal is held at ‘““H” (high), and a 1/2 divider is
made when held at “‘L”’ (low).
This port is used only when the VCOH terminal (FM in this set) i.e., pin 22 is used.
This set uses this port asa 1/4 divider.
FM OSC
SIGNAL
INPUT
Receives frequencies from 10 MHz to 130 MHz or from 10 MHz to 100 MHz both of a level
of 0.2 Vp-p minimum from the local-oscillator output, i.e., the VCO output. This input
signal is connected internally in this device through the 1/2 fixed-divider prescaler or the
1/4 fixed-divider prescaler and through the two-module prescaler composed of 1/32 and
1/33 frequency dividers to the internal programmable counter.
This terminal is pulled down to the ground level when the direct frequency-dividing sys-
tem is taken into the circuit or when the Pulse-Swallow system is used with the HF com-
mand executed, i.e., the VCOL (AM) terminal is selected.
A capacitor coupling is needed due to the inclusion of alternate current amplifiers inside
this device.