Sony ST-S3 - Page 22

22
ST-S3
Pin No. Pin Name I/O Description
48
VSS —
Ground terminal
49
WMD0 I
S-RAM wait mode setting terminal Fixed at “L” in this set
50
PAGE2 O
Page selection signal output terminal Not used (open)
51
VSS —
Ground terminal
52, 53
PAGE1, PAGE0 O
Page selection signal output terminal Not used (open)
54
BOOT I
Boot mode control signal output terminal Not used (fixed at “L”)
55
BTACT I
Boot mode state display signal output terminal Not used (open)
56
BST I
Boot trap signal input from the M61512FP (IC607)
57
MOD1 I
PLL input frequency select terminal “L”: 384fs, “H”: 256fs (fixed at “H” in this set)
58
MOD0 I
Mode setting terminal “L”: single chip mode, “H”: use prohibition (fixed at “L” in this set)
59
EXLOCK I
PLL lock error and data error flag input from the digital audio interface receiver (IC604)
60
VDDI —
Power supply terminal (+2.6V)
61
VSS —
Ground terminal
62, 63
A17, A16 O
Address signal output terminal Not used (open)
64 to 66
A15 to A13 O
Address signal output to the S-RAM (IC602)
67
GP10 O
L/R sampling clock signal (44.1 kHz) output to the D/A, A/D converter (IC605)
68
DECODE O
Decode signal output to the system controller (IC501)
69
AUDIO I
Bit 1 input terminal of channel status from the digital audio interface receiver (IC604)
70
VDDI —
Power supply terminal (+2.6V)
71
VSS —
Ground terminal
72 to 75
D15 to D12 I/O
Two-way data bus with the S-RAM (IC602)
76
VDDE —
Power supply terminal (+3.3V)
77 to 80
D11 to D8 I/O
Two-way data bus with the S-RAM (IC602)
81
VSS —
Ground terminal
82 to 85
A9, A12 to A10 O
Address signal output to the S-RAM (IC602)
86
TDO O
Simple emulation data output terminal Not used (open)
87
TMS I
Simple emulation data input start/end detection signal input terminal Not used (open)
88
XTRST I
Simple emulation asychronous break input terminal Not used (open)
89
TCK I
Simple emulation clock signal input terminal Not used (open)
90
TDI I
Simple emulation data input terminal Not used (open)
91
VSS —
Ground terminal
92 to 97
A8 to A3 O
Address signal output to the S-RAM (IC602)
98, 99
D7, D6 I/O
Two-way data bus with the S-RAM (IC602)
100
VDDI —
Power supply terminal (+2.6V)
101
VSS —
Ground terminal
102 to 105 D5 to D2 I/O
Two-way data bus with the S-RAM (IC602)
106
VDDE —
Power supply terminal (+3.3V)
107, 108
D1, D0 I/O
Two-way data bus with the S-RAM (IC602)
109, 110
A2, A1 O
Address signal output to the S-RAM (IC602)
111
VSS —
Ground terminal
112
A0 O
Address signal output to the S-RAM (IC602)
113
PM I
PLL reset signal input from the M61512FP (IC607) “L”: reset
114, 115
SDI3, SDI4 I
Audio serial data input terminal Not used (fixed at “L”)
116
SYNC I
Synchronous/asychronous selection signal input terminal
“L”: Synchronous, “H”: asynchronous (fixed at “H” in this set)
117 to 119 VSS —
Ground terminal
120
VDDI —
Power supply terminal (+2.6V)