Sony ST-S3 - Page 23

23
ST-S3
• DSP BOARD IC604 LC89056W-E (DIGITAL AUDIO INTERFACE RECEIVER)
Pin No. Pin Name I/O Description
1
DISEL I
Selection terminal of data input terminal Fixed at “L” in this set
2 DOUT O
Digital data output to the optical transceiver (IC609)
3 DIN0 I
Digital data input from the optical receiver (IC952) (for CDP-S3)
4 DIN1 I
Digital data input from the optical receiver (IC951) (for external input)
5 DIN2 I
Digital data input terminal Not used (fixed at “L”)
6DGND—
Ground terminal (digital system)
7DVDD—
Power supply terminal (+3.3V) (digital system)
8RI
VCO gain control input terminal
9 VIN I
VCO free run frequency setting input terminal
10 LPF O
PLL loop filter setting output terminal
11 AVDD —
Power supply terminal (+3.3V) (analog system)
12 AGND —
Ground terminal (analog system)
13 CKOUT O
Audio clock signal output to the CXD9617R (IC601)
14 BCK O
Bit clock signal (2.8224 MHz) output to the CXD9617R (IC601)
15
LRCK O
L/R sampling clock signal (44.1 kHz) output to the CXD9617R (IC601)
16
DATAO O
Audio serial data output to the CXD9617R (IC601)
17
XSTATE O
Source clock switching monitor output to the system controller (IC501)
18
DGND —
Ground terminal (digital system)
19
DVDD —
Power supply terminal (+3.3V) (digital system)
20
XMCK O
Oscillation clock signal output to the CXD9617R (IC601)
21
XOUT O
System clock output terminal (13.5 MHz)
22
XIN I
System clock input terminal (13.5 MHz)
23
EMPHA O
Emphasis information of channel status output terminal Not used (open)
24
AUDIO O
Bit 1 output terminal of channel status to the CXD9617R (IC601)
25 CSFLAG O
Top 40 bit renovation flag output terminal of channel status Not used (open)
26 to 28 F0 to F2 O
Input frequency calculation result output terminal Not used (open)
29 VF O
Validity flag output terminal Not used (open)
30
DVDD —
Power supply terminal (+3.3V) (digital system)
31
DGND —
Ground terminal (digital system)
32
ERR9P O
Nine times continuance data transmission error flag output terminal Not used (open)
33
BPSYNC O
Non-PCM burst and preamble sync signal output terminal Not used (open)
34 ERROR O
PLL lock error and data error flag output to the system controller (IC501)
35
DO O
Read data output to the system controller (IC501)
36
DI I
Write data input from the system controller (IC501)
37
CE I
Chip enable signal input from the system controller (IC501)
38
CL I
Clock signal input from the system controller (IC501)
39
XSEL I
Selection input terminal of vibrator frequency terminal Fixed at “H” in this set
40
MODE0 I
Mode setting input terminal Fixed at “H” in this set
41
MODE1 I
Mode setting input terminal Fixed at “H” in this set
42
DGND —
Ground terminal (digital system)
43
DVDD —
Power supply terminal (+3.3V) (digital system)
44
DOSEL0 I
Output data format selection signal input terminal Fixed at “L” in this set
45
DOSEL1 I
Output data format selection signal input terminal Fixed at “L” in this set
46
CKSEL0 I
Output clock selection signal input terminal Fixed at “L” in this set
47
CKSEL1 I
Output clock selection signal input terminal Fixed at “L” in this set
48
XMODE I
System reset signal input from the M61512FP (IC607)