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ST UC2842B - Page 5

ST UC2842B
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Figure 1: Open Loop Test Circuit.
R
T
A2N2222
4.7K
1K
ERROR AMP.
ADJUST
4.7K
5K
I
SENSE
ADJUST
100K
COMP
V
FB
I
SENSE
R
T
/C
T
1
2
3
4
C
T
7
6
5
8
V
REF
V
i
OUTPUT
GROUND
0.1µF
0.1µF
V
REF
V
i
OUTPUT
GROUND
1W
1K
D95IN343
High peak currents associated with capacitive loads
necessitate careful grounding techniques. Timing
and bypass capacitors should be connected close
to pin 5 in a single point ground. The transistor and
5 K potentiometer are used to sample the oscillator
waveform and apply an adjustable ramp to pin 3.
10K 20K 30K 50K 100K 200K 300K 500K f
OSC
(KHz)
1
2
5
10
20
50
D95IN333
C
T
=10nF
C
T
=5nF
C
T
=2nF
C
T
=1nF
C
T
=500pF
C
T
=200pF
C
T
=100pF
V
i
=15V
T
A
=25˚C
RT
(K)
0.8
Figure 2: Timing Resistor vs. Oscillator Fre-
quency
10K 20K 30K 50K 100K 200K 300K 500K fOSC(KHz)
1
2
3
5
10
20
30
50
%
C
T
=10nF
C
T
=5nF
C
T
=2nF
C
T
=1nF
C
T
=500pF
C
T
=200pF
C
T
=100pF
D95IN334
V
i
=15V
T
A
=25˚C
Figure 3: Output Dead-Time vs. Oscillator Fre-
quency
UC2842B
UC2842B/3B/4B/5B - UC3842B/3B/4B/5B
5/15

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