Independent Watchdog (IWDG)
The IWDG is just the ordinary watchdog timer we usually find in any modern micro. The purpose of
this timer is to recover a micro from an unanticipated event that may result in unresponsive or erratic
behaviour. As the name suggests, this timer does not share anything with any other internal hardware
peripheral and is clocked by LSI (128kHz) only. Thus, it is invulnerable to main clock (HSE or HSI) failure.
The IWDG works by decrementing a counter, counting time in the process. When the counter hits
zero, a reset is issued. Usually we would want that this reset never occurs and so the counter is
periodically updated in the application firmware. If for some reason, the counter is not refreshed, a
reset will occur, recovering the MCU from a disastrous situation.
Configuring the IWDG is very easy with SPL. There are certain steps to follow but SPL manages them
well internally. All we’ll need is to configure the IWDG and reload it periodically before time runs out.
The formula required to calculate timeout is given below:
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