Supermicro X12SCA-F - Page 73

Chapter 4: UEFI BIOS
73
• Processor Cores
• Hyper Threading Technology
• VMX
• SMX/TXT
• 64-bit
• EIST Technology
• CPU C3 state
• CPU C6 state
• CPU C7 state
• CPU C8 state
• CPU C9 state
• CPU C10 state
• L1 Data Cache
• L1 Instruction Cache
• L2 Cache
• L3 Cache
• L4 Cache
C6DRAM (Available when supported by the CPU)
This feature enables moving DRAM contents to PRM memory when the CPU is in a C6
state. The options are Disabled and Enabled.
Hardware Prefetcher (Available when supported by the CPU)
If set to Enabled, the hardware prefetcher will prefetch streams of data and instructions
from the main memory to the L2 cache to improve CPU performance. The options are
Disabled and Enabled.
Adjacent Cache Line Prefetch (Available when supported by the CPU)
The CPU prefetches the cache line for 64 bytes if this feature is set to Disabled. The CPU
prefetches both cache lines for 128 bytes as comprised if this feature is set to Enabled.